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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-03-03 10:39:47 +00:00
parent 6e38e236f8
commit fba71bd182
3 changed files with 107 additions and 113 deletions
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3
fpga_interchange/arch.cc
View File

@ -723,7 +723,8 @@ bool Arch::route()
return result;
}
bool Arch::route_vcc_to_unused_lut_pins() {
bool Arch::route_vcc_to_unused_lut_pins()
{
std::string router = str_or_default(settings, id("router"), defaultRouter);
// Fixup LUT vcc pins.

62
fpga_interchange/luts.cc
View File

@ -19,16 +19,15 @@
#include "nextpnr.h"
#include "luts.h"
#include "log.h"
#include "luts.h"
NEXTPNR_NAMESPACE_BEGIN
bool rotate_and_merge_lut_equation(std::vector<LogicLevel> * result,
const LutBel & lut_bel,
const nextpnr::DynamicBitarray<> &old_equation,
const std::vector<int32_t> &pin_map,
uint32_t used_pins) {
bool rotate_and_merge_lut_equation(std::vector<LogicLevel> *result, const LutBel &lut_bel,
const nextpnr::DynamicBitarray<> &old_equation, const std::vector<int32_t> &pin_map,
uint32_t used_pins)
{
// pin_map maps pin indicies from the old pin to the new pin.
// So a reversal of a LUT4 would have a pin map of:
// pin_map[0] = 3;
@ -54,7 +53,6 @@ bool rotate_and_merge_lut_equation(std::vector<LogicLevel> * result,
continue;
}
auto cell_pin_idx = pin_map[bel_pin_idx];
// Is this BEL pin used for this cell?
@ -92,8 +90,10 @@ bool rotate_and_merge_lut_equation(std::vector<LogicLevel> * result,
static constexpr bool kCheckOutputEquation = true;
struct LutPin {
struct LutPinUser {
struct LutPin
{
struct LutPinUser
{
size_t cell_idx;
size_t cell_pin_idx;
};
@ -104,7 +104,8 @@ struct LutPin {
int32_t min_pin = -1;
int32_t max_pin = -1;
void add_user(const LutBel & lut_bel, size_t cell_idx, size_t cell_pin_idx) {
void add_user(const LutBel &lut_bel, size_t cell_idx, size_t cell_pin_idx)
{
if (min_pin < 0) {
min_pin = lut_bel.min_pin;
max_pin = lut_bel.max_pin;
@ -118,12 +119,11 @@ struct LutPin {
users.back().cell_pin_idx = cell_pin_idx;
}
bool operator < (const LutPin & other) const {
return max_pin < other.max_pin;
}
bool operator<(const LutPin &other) const { return max_pin < other.max_pin; }
};
bool LutMapper::remap_luts(const Context *ctx) {
bool LutMapper::remap_luts(const Context *ctx)
{
std::unordered_map<NetInfo *, LutPin> lut_pin_map;
std::vector<const LutBel *> lut_bels;
lut_bels.resize(cells.size());
@ -131,7 +131,8 @@ bool LutMapper::remap_luts(const Context *ctx) {
for (size_t cell_idx = 0; cell_idx < cells.size(); ++cell_idx) {
const CellInfo *cell = cells[cell_idx];
#ifdef DEBUG_LUT_ROTATION
log_info("Mapping %s %s eq = %s at %s\n", cell->type.c_str(ctx), cell->name.c_str(ctx), cell->params.at(ctx->id("INIT")).c_str(), ctx->nameOfBel(cell->bel));
log_info("Mapping %s %s eq = %s at %s\n", cell->type.c_str(ctx), cell->name.c_str(ctx),
cell->params.at(ctx->id("INIT")).c_str(), ctx->nameOfBel(cell->bel));
#endif
auto &bel_data = bel_info(ctx->chip_info, cell->bel);
@ -155,8 +156,8 @@ bool LutMapper::remap_luts(const Context *ctx) {
// Trival conflict, more nets entering element than pins are
// available!
#ifdef DEBUG_LUT_ROTATION
log_info("Trival failure %zu > %zu, %zu %zu\n",
lut_pin_map.size(), element.pins.size(), element.width, element.lut_bels.size());
log_info("Trival failure %zu > %zu, %zu %zu\n", lut_pin_map.size(), element.pins.size(), element.width,
element.lut_bels.size());
#endif
return false;
}
@ -190,11 +191,8 @@ bool LutMapper::remap_luts(const Context *ctx) {
size_t pin_idx = cell_pin_idx.cell_pin_idx;
IdString bel_pin = lut_bels[cell_idx]->pins[net_idx];
#ifdef DEBUG_LUT_ROTATION
log_info("%s %s %s => %s (%s)\n",
cells[cell_idx]->type.c_str(ctx),
cells[cell_idx]->name.c_str(ctx),
cells[cell_idx]->lut_cell.pins[pin_idx].c_str(ctx),
bel_pin.c_str(ctx),
log_info("%s %s %s => %s (%s)\n", cells[cell_idx]->type.c_str(ctx), cells[cell_idx]->name.c_str(ctx),
cells[cell_idx]->lut_cell.pins[pin_idx].c_str(ctx), bel_pin.c_str(ctx),
lut_pin.net->name.c_str(ctx));
#endif
if (net_pins[net_idx] == IdString()) {
@ -214,14 +212,12 @@ bool LutMapper::remap_luts(const Context *ctx) {
for (size_t cell_idx = 0; cell_idx < cells.size(); ++cell_idx) {
const CellInfo *cell = cells[cell_idx];
auto &lut_bel = *lut_bels[cell_idx];
if(!rotate_and_merge_lut_equation(&equation_result,
lut_bel, cell->lut_cell.equation, bel_to_cell_pin_remaps[cell_idx], used_pins)) {
if (!rotate_and_merge_lut_equation(&equation_result, lut_bel, cell->lut_cell.equation,
bel_to_cell_pin_remaps[cell_idx], used_pins)) {
#ifdef DEBUG_LUT_ROTATION
log_info("Failed to find a solution!\n");
for (auto *cell : cells) {
log_info("%s %s : %s\b\n",
cell->type.c_str(ctx),
cell->name.c_str(ctx),
log_info("%s %s : %s\b\n", cell->type.c_str(ctx), cell->name.c_str(ctx),
cell->params.at(ctx->id("INIT")).c_str());
}
#endif
@ -274,12 +270,9 @@ bool LutMapper::remap_luts(const Context *ctx) {
return true;
}
void check_equation(
const LutCell & lut_cell,
const std::unordered_map<IdString, IdString> &cell_to_bel_map,
const LutBel & lut_bel,
const std::vector<LogicLevel> &equation,
uint32_t used_pins) {
void check_equation(const LutCell &lut_cell, const std::unordered_map<IdString, IdString> &cell_to_bel_map,
const LutBel &lut_bel, const std::vector<LogicLevel> &equation, uint32_t used_pins)
{
std::vector<int8_t> pin_map;
pin_map.resize(lut_bel.pins.size(), -1);
@ -338,7 +331,8 @@ void check_equation(
}
}
void LutElement::compute_pin_order() {
void LutElement::compute_pin_order()
{
pins.clear();
pin_to_index.clear();

29
fpga_interchange/luts.h
View File

@ -31,13 +31,15 @@ NEXTPNR_NAMESPACE_BEGIN
struct CellInfo;
struct Context;
enum LogicLevel {
enum LogicLevel
{
LL_Zero,
LL_One,
LL_DontCare
};
struct LutCell {
struct LutCell
{
// LUT cell pins for equation, LSB first.
std::vector<IdString> pins;
std::unordered_set<IdString> lut_pins;
@ -45,7 +47,8 @@ struct LutCell {
nextpnr::DynamicBitarray<> equation;
};
struct LutBel {
struct LutBel
{
// LUT BEL pins to LUT array index.
std::vector<IdString> pins;
std::unordered_map<IdString, size_t> pin_to_index;
@ -61,14 +64,11 @@ struct LutBel {
// Work forward from cell definition and cell -> bel pin map and check that
// equation is valid.
void check_equation(
const LutCell & lut_cell,
const std::unordered_map<IdString, IdString> &cell_to_bel_map,
const LutBel & lut_bel,
const std::vector<LogicLevel> &equation,
uint32_t used_pins);
void check_equation(const LutCell &lut_cell, const std::unordered_map<IdString, IdString> &cell_to_bel_map,
const LutBel &lut_bel, const std::vector<LogicLevel> &equation, uint32_t used_pins);
struct LutElement {
struct LutElement
{
size_t width;
std::unordered_map<IdString, LutBel> lut_bels;
@ -78,7 +78,8 @@ struct LutElement {
std::unordered_map<IdString, size_t> pin_to_index;
};
struct LutMapper {
struct LutMapper
{
LutMapper(const LutElement &element) : element(element) {}
const LutElement &element;
@ -90,10 +91,8 @@ struct LutMapper {
// Rotate and merge a LUT equation into an array of levels.
//
// If a conflict arises, return false and result is in an indeterminate state.
bool rotate_and_merge_lut_equation(std::vector<LogicLevel> * result,
const LutBel & lut_bel,
const nextpnr::DynamicBitarray<> &old_equation,
const std::vector<size_t> &pin_map,
bool rotate_and_merge_lut_equation(std::vector<LogicLevel> *result, const LutBel &lut_bel,
const nextpnr::DynamicBitarray<> &old_equation, const std::vector<size_t> &pin_map,
uint32_t used_pins);
NEXTPNR_NAMESPACE_END