Merge pull request #895 from galibert/master
Sync with the current state of mistral
This commit is contained in:
gatecat
GitHub
commit
fbeef2b8c2
2
.github/workflows/mistral_ci.yml
vendored
2
.github/workflows/mistral_ci.yml
vendored
@ -21,7 +21,7 @@ jobs:
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- name: Execute build nextpnr
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env:
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MISTRAL_PATH: ${{ github.workspace }}/deps/mistral
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MISTRAL_REVISION: e039b595529ab573d9cb01c64ef927f9d81d63ce
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MISTRAL_REVISION: 0c2ab2b2c6af33fea1c20349be2e0068366ed615
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run: |
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source ./.github/ci/build_mistral.sh
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get_dependencies
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@ -43,6 +43,42 @@ void IdString::initialize_arch(const BaseCtx *ctx)
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#undef X
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}
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CycloneV::rnode_t Arch::find_rnode(CycloneV::block_type_t bt, int x, int y, CycloneV::port_type_t port, int bi, int pi) const
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{
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auto pn1 = CycloneV::pnode(bt, x, y, port, bi, pi);
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auto rn1 = cyclonev->pnode_to_rnode(pn1);
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if(rn1)
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return rn1;
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if(bt == CycloneV::GPIO) {
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auto pn2 = cyclonev->p2p_to(pn1);
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if(!pn2) {
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auto pnv = cyclonev->p2p_from(pn1);
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if(!pnv.empty())
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pn2 = pnv[0];
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}
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auto pn3 = cyclonev->hmc_get_bypass(pn2);
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auto rn2 = cyclonev->pnode_to_rnode(pn3);
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return rn2;
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}
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return 0;
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}
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WireId Arch::get_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi) const
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{
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auto rn = find_rnode(bt, x, y, port, bi, pi);
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if(rn)
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return WireId(rn);
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log_error("Trying to connect unknown node %s\n", CycloneV::pn2s(CycloneV::pnode(bt, x, y, port, bi, pi)).c_str());
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}
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bool Arch::has_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi) const
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{
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return find_rnode(bt, x, y, port, bi, pi) != 0;
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}
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Arch::Arch(ArchArgs args)
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{
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this->args = args;
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@ -461,10 +461,9 @@ struct Arch : BaseArch<ArchRanges>
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void add_bel_pin(BelId bel, IdString pin, PortType dir, WireId wire);
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WireId get_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi = -1) const
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{
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return WireId(cyclonev->pnode_to_rnode(CycloneV::pnode(bt, x, y, port, bi, pi)));
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}
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CycloneV::rnode_t find_rnode(CycloneV::block_type_t bt, int x, int y, CycloneV::port_type_t port, int bi = -1, int pi = -1) const;
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WireId get_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi = -1) const;
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bool has_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi = -1) const;
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void create_lab(int x, int y, bool is_mlab); // lab.cc
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void create_gpio(int x, int y); // io.cc
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@ -562,7 +561,6 @@ struct Arch : BaseArch<ArchRanges>
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// -------------------------------------------------
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void init_base_bitstream(); // base_bitstream.cc
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void build_bitstream(); // bitstream.cc
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};
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@ -1,100 +0,0 @@
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/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2021 gatecat <gatecat@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "log.h"
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#include "nextpnr.h"
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NEXTPNR_NAMESPACE_BEGIN
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namespace {
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// Device-specific default config for the sx120f die
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void default_sx120f(CycloneV *cv)
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{
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// Default PMA config?
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cv->bmux_m_set(CycloneV::PMA3, CycloneV::xy2pos(0, 11), CycloneV::FFPLL_IQCLK_DIRECTION, 0, CycloneV::TRISTATE);
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cv->bmux_m_set(CycloneV::PMA3, CycloneV::xy2pos(0, 11), CycloneV::FFPLL_IQCLK_DIRECTION, 1, CycloneV::TRISTATE);
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cv->bmux_m_set(CycloneV::PMA3, CycloneV::xy2pos(0, 23), CycloneV::FFPLL_IQCLK_DIRECTION, 0, CycloneV::DOWN);
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cv->bmux_m_set(CycloneV::PMA3, CycloneV::xy2pos(0, 23), CycloneV::FFPLL_IQCLK_DIRECTION, 1, CycloneV::UP);
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cv->bmux_m_set(CycloneV::PMA3, CycloneV::xy2pos(0, 35), CycloneV::FFPLL_IQCLK_DIRECTION, 0, CycloneV::UP);
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cv->bmux_m_set(CycloneV::PMA3, CycloneV::xy2pos(0, 35), CycloneV::FFPLL_IQCLK_DIRECTION, 1, CycloneV::UP);
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cv->bmux_b_set(CycloneV::PMA3, CycloneV::xy2pos(0, 35), CycloneV::FPLL_DRV_EN, 0, 0);
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cv->bmux_m_set(CycloneV::PMA3, CycloneV::xy2pos(0, 35), CycloneV::HCLK_TOP_OUT_DRIVER, 0, CycloneV::TRISTATE);
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// Default PLL config
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cv->bmux_b_set(CycloneV::FPLL, CycloneV::xy2pos(0, 73), CycloneV::PL_AUX_ATB_EN0, 0, 1);
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cv->bmux_b_set(CycloneV::FPLL, CycloneV::xy2pos(0, 73), CycloneV::PL_AUX_ATB_EN0_PRECOMP, 0, 1);
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cv->bmux_b_set(CycloneV::FPLL, CycloneV::xy2pos(0, 73), CycloneV::PL_AUX_ATB_EN1, 0, 1);
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cv->bmux_b_set(CycloneV::FPLL, CycloneV::xy2pos(0, 73), CycloneV::PL_AUX_ATB_EN1_PRECOMP, 0, 1);
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cv->bmux_b_set(CycloneV::FPLL, CycloneV::xy2pos(0, 73), CycloneV::PL_AUX_BG_KICKSTART, 0, 1);
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cv->bmux_b_set(CycloneV::FPLL, CycloneV::xy2pos(0, 73), CycloneV::PL_AUX_VBGMON_POWERDOWN, 0, 1);
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// Default TERM config
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cv->bmux_b_set(CycloneV::TERM, CycloneV::xy2pos(89, 34), CycloneV::INTOSC_2_EN, 0, 0);
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// TODO: what if these pins are used? where do these come from
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for (int z = 0; z < 4; z++) {
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cv->bmux_m_set(CycloneV::GPIO, CycloneV::xy2pos(89, 43), CycloneV::IOCSR_STD, z, CycloneV::NVR_LOW);
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cv->bmux_m_set(CycloneV::GPIO, CycloneV::xy2pos(89, 66), CycloneV::IOCSR_STD, z, CycloneV::NVR_LOW);
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}
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for (int y : {38, 44, 51, 58, 65, 73, 79}) {
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// TODO: Why only these upper DQS? is there a pattern?
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cv->bmux_b_set(CycloneV::DQS16, CycloneV::xy2pos(89, y), CycloneV::RB_2X_CLK_DQS_INV, 0, 1);
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cv->bmux_b_set(CycloneV::DQS16, CycloneV::xy2pos(89, y), CycloneV::RB_ACLR_LFIFO_EN, 0, 1);
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cv->bmux_b_set(CycloneV::DQS16, CycloneV::xy2pos(89, y), CycloneV::RB_LFIFO_BYPASS, 0, 0);
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}
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// Discover these mux values using
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// grep 'i [_A-Z0-9.]* 1' empty.bt
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cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 12), 69), true);
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cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 13), 4), true);
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cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 34), 69), true);
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cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 35), 4), true);
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cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 37), 31), true);
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cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 40), 43), true);
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cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 46), 69), true);
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cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 47), 43), true);
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cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 53), 69), true);
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cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 54), 4), true);
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cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 73), 68), true);
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cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(9, 18), 66), true);
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cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(9, 20), 8), true);
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cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(9, 27), 69), true);
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cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(9, 28), 43), true);
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cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(9, 59), 66), true);
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cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(9, 61), 8), true);
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cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(9, 68), 69), true);
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cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(9, 69), 43), true);
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for (int z = 10; z <= 45; z++)
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cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(51, 80), z), true);
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}
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} // namespace
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void Arch::init_base_bitstream()
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{
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switch (cyclonev->current_model()->variant.die.type) {
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case CycloneV::SX120F:
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default_sx120f(cyclonev);
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break;
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default:
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log_error("FIXME: die type %s currently unsupported for bitgen.\n",
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cyclonev->current_model()->variant.die.name);
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}
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}
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NEXTPNR_NAMESPACE_END
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@ -29,129 +29,41 @@ struct MistralBitgen
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Context *ctx;
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CycloneV *cv;
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void init()
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using rnode_t = CycloneV::rnode_t;
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using pnode_t = CycloneV::pnode_t;
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using pos_t = CycloneV::pos_t;
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using block_type_t = CycloneV::block_type_t;
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using port_type_t = CycloneV::port_type_t;
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rnode_t find_rnode(block_type_t bt, pos_t pos, port_type_t port, int bi = -1, int pi = -1) const
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{
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ctx->init_base_bitstream();
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// Default options
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cv->opt_b_set(CycloneV::ALLOW_DEVICE_WIDE_OUTPUT_ENABLE_DIS, true);
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if (!ctx->setting<bool>("compress_rbf", false))
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auto pn1 = CycloneV::pnode(bt, pos, port, bi, pi);
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auto rn1 = cv->pnode_to_rnode(pn1);
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if(rn1)
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return rn1;
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if(bt == CycloneV::GPIO) {
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auto pn2 = cv->p2p_to(pn1);
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if(!pn2) {
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auto pnv = cv->p2p_from(pn1);
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if(!pnv.empty())
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pn2 = pnv[0];
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}
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auto pn3 = cv->hmc_get_bypass(pn2);
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auto rn2 = cv->pnode_to_rnode(pn3);
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return rn2;
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}
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return 0;
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}
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void options()
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{
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if (!ctx->setting<bool>("compress_rbf", false)) {
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cv->opt_b_set(CycloneV::COMPRESSION_DIS, true);
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cv->opt_n_set(CycloneV::CRC_DIVIDE_ORDER, 8);
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cv->opt_b_set(CycloneV::CVP_CONF_DONE_EN, true);
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cv->opt_b_set(CycloneV::DEVICE_WIDE_RESET_EN, true);
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cv->opt_n_set(CycloneV::DRIVE_STRENGTH, 8);
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cv->opt_b_set(CycloneV::IOCSR_READY_FROM_CSR_DONE_EN, true);
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cv->opt_b_set(CycloneV::NCEO_DIS, true);
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cv->opt_b_set(CycloneV::OCT_DONE_DIS, true);
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cv->opt_r_set(CycloneV::OPT_A, 0x1dff);
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if (!ctx->setting<bool>("compress_rbf", false))
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cv->opt_r_set(CycloneV::OPT_B, 0xffffff40adffffffULL);
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else
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} else
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cv->opt_r_set(CycloneV::OPT_B, 0xffffff402dffffffULL);
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cv->opt_b_set(CycloneV::RELEASE_CLEARS_BEFORE_TRISTATES_DIS, true);
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cv->opt_b_set(CycloneV::RETRY_CONFIG_ON_ERROR_EN, true);
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cv->opt_r_set(CycloneV::START_UP_CLOCK, 0x3F);
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// Default inversion
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write_default_inv();
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}
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void write_default_inv()
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{
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// Some PNODEs are inverted by default. Set them up here.
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for (const auto &pn2r : cv->get_all_p2r()) {
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const auto &pn = pn2r.first;
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auto pt = CycloneV::pn2pt(pn);
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auto pi = CycloneV::pn2pi(pn);
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switch (CycloneV::pn2bt(pn)) {
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case CycloneV::HMC: {
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// HMC OE are inverted to set OE=0, i.e. unused pins floating
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// TODO: handle the case when we are using the HMC or HMC bypass
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std::string name(CycloneV::port_type_names[pt]);
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if (name.compare(0, 5, "IOINT") != 0 || name.compare(name.size() - 2, 2, "OE") != 0)
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continue;
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cv->inv_set(pn2r.second, true);
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break;
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};
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// HPS IO - TODO: what about when we actually support the HPS primitives?
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case CycloneV::HPS_BOOT: {
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switch (pt) {
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case CycloneV::CSEL_EN:
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case CycloneV::BSEL_EN:
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case CycloneV::BOOT_FROM_FPGA_READY:
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case CycloneV::BOOT_FROM_FPGA_ON_FAILURE:
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cv->inv_set(pn2r.second, true);
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break;
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case CycloneV::CSEL:
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if (pi < 2)
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cv->inv_set(pn2r.second, true);
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break;
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case CycloneV::BSEL:
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if (pi < 3)
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cv->inv_set(pn2r.second, true);
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break;
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default:
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break;
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};
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break;
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};
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case CycloneV::HPS_CROSS_TRIGGER: {
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if (pt == CycloneV::CLK_EN)
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cv->inv_set(pn2r.second, true);
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break;
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};
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case CycloneV::HPS_TEST: {
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if (pt == CycloneV::CFG_DFX_BYPASS_ENABLE)
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cv->inv_set(pn2r.second, true);
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break;
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};
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case CycloneV::GPIO: {
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// Ignore GPIO used by the design
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BelId bel = ctx->bel_by_block_idx(CycloneV::pn2x(pn), CycloneV::pn2y(pn), id_MISTRAL_IO,
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CycloneV::pn2bi(pn));
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if (bel != BelId() && ctx->getBoundBelCell(bel) != nullptr)
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continue;
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// Bonded IO invert OEIN.1 which disables the output buffer and floats the IO
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// Unbonded IO invert OEIN.0 which enables the output buffer, and {DATAIN.[0123]} to drive a constant
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// GND, presumably for power/EMI reasons
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bool is_bonded = cv->pin_find_pnode(pn) != nullptr;
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if (is_bonded && (pt != CycloneV::OEIN || pi != 1))
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continue;
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if (!is_bonded && (pt != CycloneV::DATAIN) && (pt != CycloneV::OEIN || pi != 0))
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continue;
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cv->inv_set(pn2r.second, true);
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break;
|
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};
|
||||
case CycloneV::FPLL: {
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if (pt == CycloneV::EXTSWITCH0 || (pt == CycloneV::CLKEN && pi < 2))
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cv->inv_set(pn2r.second, true);
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break;
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};
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default:
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break;
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}
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}
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}
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void write_dqs()
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{
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for (auto pos : cv->dqs16_get_pos()) {
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int x = CycloneV::pos2x(pos), y = CycloneV::pos2y(pos);
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// DQS bypass for used output pins
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for (int z = 0; z < 16; z++) {
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int ioy = y + (z / 4) - 2;
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if (ioy < 0 || ioy >= int(cv->get_tile_sy()))
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continue;
|
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BelId bel = ctx->bel_by_block_idx(x, ioy, id_MISTRAL_IO, z % 4);
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if (bel == BelId())
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continue;
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CellInfo *ci = ctx->getBoundBelCell(bel);
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if (ci == nullptr || (ci->type != id_MISTRAL_IO && ci->type != id_MISTRAL_OB))
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continue; // not an output
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cv->bmux_m_set(CycloneV::DQS16, pos, CycloneV::INPUT_REG4_SEL, z, CycloneV::SEL_LOCKED_DPA);
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cv->bmux_r_set(CycloneV::DQS16, pos, CycloneV::RB_T9_SEL_EREG_CFF_DELAY, z, 0x1f);
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}
|
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}
|
||||
}
|
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|
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void write_routing()
|
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@ -182,12 +94,19 @@ struct MistralBitgen
|
||||
if (is_output) {
|
||||
cv->bmux_m_set(CycloneV::GPIO, pos, CycloneV::DRIVE_STRENGTH, bi, CycloneV::V3P3_LVTTL_16MA_LVCMOS_2MA);
|
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cv->bmux_m_set(CycloneV::GPIO, pos, CycloneV::IOCSR_STD, bi, CycloneV::DIS);
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||||
|
||||
// Output gpios must also bypass things in the associated dqs
|
||||
auto dqs = cv->p2p_to(CycloneV::pnode(CycloneV::GPIO, pos, CycloneV::PNONE, bi, -1));
|
||||
if(dqs) {
|
||||
cv->bmux_m_set(CycloneV::DQS16, CycloneV::pn2p(dqs), CycloneV::INPUT_REG4_SEL, CycloneV::pn2bi(dqs), CycloneV::SEL_LOCKED_DPA);
|
||||
cv->bmux_r_set(CycloneV::DQS16, CycloneV::pn2p(dqs), CycloneV::RB_T9_SEL_EREG_CFF_DELAY, CycloneV::pn2bi(dqs), 0x1f);
|
||||
}
|
||||
}
|
||||
// There seem to be two mirrored OEIN inversion bits for constant OE for inputs/outputs. This might be to
|
||||
// prevent a single bitflip from turning inputs to outputs and messing up other devices on the boards, notably
|
||||
// ECP5 does similar. OEIN.0 inverted for outputs; OEIN.1 for inputs
|
||||
cv->inv_set(cv->pnode_to_rnode(CycloneV::pnode(CycloneV::GPIO, pos, CycloneV::OEIN, bi, is_output ? 0 : 1)),
|
||||
true);
|
||||
cv->inv_set(find_rnode(CycloneV::GPIO, pos, CycloneV::OEIN, bi, 0), is_output);
|
||||
cv->inv_set(find_rnode(CycloneV::GPIO, pos, CycloneV::OEIN, bi, 1), !is_output);
|
||||
}
|
||||
|
||||
void write_clkbuf_cell(CellInfo *ci, int x, int y, int bi)
|
||||
@ -392,9 +311,8 @@ struct MistralBitgen
|
||||
void run()
|
||||
{
|
||||
cv->clear();
|
||||
init();
|
||||
options();
|
||||
write_routing();
|
||||
write_dqs();
|
||||
write_cells();
|
||||
write_labs();
|
||||
}
|
||||
|
||||
@ -30,10 +30,12 @@ void Arch::create_gpio(int x, int y)
|
||||
WireId pad = add_wire(x, y, id(stringf("PAD[%d]", z)));
|
||||
BelId bel = add_bel(x, y, id(stringf("IO[%d]", z)), id_MISTRAL_IO);
|
||||
add_bel_pin(bel, id_PAD, PORT_INOUT, pad);
|
||||
// FIXME: is the port index of zero always correct?
|
||||
add_bel_pin(bel, id_I, PORT_IN, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAOUT, 0));
|
||||
add_bel_pin(bel, id_OE, PORT_IN, get_port(CycloneV::GPIO, x, y, z, CycloneV::OEIN, 0));
|
||||
add_bel_pin(bel, id_O, PORT_OUT, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAIN, 0));
|
||||
if(has_port(CycloneV::GPIO, x, y, z, CycloneV::DATAOUT, 0)) {
|
||||
// FIXME: is the port index of zero always correct?
|
||||
add_bel_pin(bel, id_I, PORT_IN, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAOUT, 0));
|
||||
add_bel_pin(bel, id_OE, PORT_IN, get_port(CycloneV::GPIO, x, y, z, CycloneV::OEIN, 0));
|
||||
add_bel_pin(bel, id_O, PORT_OUT, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAIN, 0));
|
||||
}
|
||||
bel_data(bel).block_index = z;
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user