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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-04-12 10:26:39 +01:00
parent b5731cee02
commit fc15105643
8 changed files with 134 additions and 133 deletions
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3
fpga_interchange/arch.cc
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@ -1972,7 +1972,8 @@ void Arch::explain_bel_status(BelId bel) const
site.explain(getCtx()); site.explain(getCtx());
} }
DelayQuad Arch::getPipDelay(PipId pip) const { DelayQuad Arch::getPipDelay(PipId pip) const
{
// FIXME: Implement when adding timing-driven place and route. // FIXME: Implement when adding timing-driven place and route.
const auto &pip_data = pip_info(chip_info, pip); const auto &pip_data = pip_info(chip_info, pip);

2
fpga_interchange/arch.h
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@ -38,8 +38,8 @@
#include "chipdb.h" #include "chipdb.h"
#include "dedicated_interconnect.h" #include "dedicated_interconnect.h"
#include "lookahead.h" #include "lookahead.h"
#include "site_router.h"
#include "pseudo_pip_model.h" #include "pseudo_pip_model.h"
#include "site_router.h"
#include "site_routing_cache.h" #include "site_routing_cache.h"
NEXTPNR_NAMESPACE_BEGIN NEXTPNR_NAMESPACE_BEGIN

11
fpga_interchange/luts.cc
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@ -17,11 +17,10 @@
* *
*/ */
#include "luts.h" #include "luts.h"
#include "nextpnr.h"
#include "log.h" #include "log.h"
#include "nextpnr.h"
//#define DEBUG_LUT_ROTATION //#define DEBUG_LUT_ROTATION
@ -131,8 +130,8 @@ struct LutPin
bool operator<(const LutPin &other) const { return max_pin < other.max_pin; } bool operator<(const LutPin &other) const { return max_pin < other.max_pin; }
}; };
uint32_t LutMapper::check_wires(const Context *ctx) const
uint32_t LutMapper::check_wires(const Context *ctx) const { {
// Unlike the 3 argument version of check_wires, this version needs to // Unlike the 3 argument version of check_wires, this version needs to
// calculate following data based on current cell pin mapping, etc: // calculate following data based on current cell pin mapping, etc:
// //
@ -149,7 +148,6 @@ uint32_t LutMapper::check_wires(const Context *ctx) const {
for (size_t cell_idx = 0; cell_idx < cells.size(); ++cell_idx) { for (size_t cell_idx = 0; cell_idx < cells.size(); ++cell_idx) {
const CellInfo *cell = cells[cell_idx]; const CellInfo *cell = cells[cell_idx];
auto &bel_data = bel_info(ctx->chip_info, cell->bel); auto &bel_data = bel_info(ctx->chip_info, cell->bel);
IdString bel_name(bel_data.name); IdString bel_name(bel_data.name);
auto &lut_bel = element.lut_bels.at(bel_name); auto &lut_bel = element.lut_bels.at(bel_name);
@ -169,8 +167,7 @@ uint32_t LutMapper::check_wires(const Context *ctx) const {
} }
HashTables::HashSet<const LutBel *> blocked_luts; HashTables::HashSet<const LutBel *> blocked_luts;
return check_wires(bel_to_cell_pin_remaps, lut_bels, used_pins, return check_wires(bel_to_cell_pin_remaps, lut_bels, used_pins, &blocked_luts);
&blocked_luts);
} }
uint32_t LutMapper::check_wires(const std::vector<std::vector<int32_t>> &bel_to_cell_pin_remaps, uint32_t LutMapper::check_wires(const std::vector<std::vector<int32_t>> &bel_to_cell_pin_remaps,

41
fpga_interchange/pseudo_pip_model.cc
View File

@ -26,7 +26,8 @@
NEXTPNR_NAMESPACE_BEGIN NEXTPNR_NAMESPACE_BEGIN
void PseudoPipData::init_tile_type(const Context *ctx, int32_t tile_type) { void PseudoPipData::init_tile_type(const Context *ctx, int32_t tile_type)
{
if (max_pseudo_pip_for_tile_type.count(tile_type)) { if (max_pseudo_pip_for_tile_type.count(tile_type)) {
return; return;
} }
@ -166,21 +167,23 @@ void PseudoPipData::init_tile_type(const Context *ctx, int32_t tile_type) {
max_pseudo_pip_for_tile_type[tile_type] = max_pseudo_pip_index; max_pseudo_pip_for_tile_type[tile_type] = max_pseudo_pip_index;
} }
const std::vector<size_t> &PseudoPipData::get_possible_sites_for_pip(const Context *ctx, PipId pip) const { const std::vector<size_t> &PseudoPipData::get_possible_sites_for_pip(const Context *ctx, PipId pip) const
{
int32_t tile_type = ctx->chip_info->tiles[pip.tile].type; int32_t tile_type = ctx->chip_info->tiles[pip.tile].type;
return possibles_sites_for_pip.at(std::make_pair(tile_type, pip.index)); return possibles_sites_for_pip.at(std::make_pair(tile_type, pip.index));
} }
size_t PseudoPipData::get_max_pseudo_pip(int32_t tile_type) const { size_t PseudoPipData::get_max_pseudo_pip(int32_t tile_type) const { return max_pseudo_pip_for_tile_type.at(tile_type); }
return max_pseudo_pip_for_tile_type.at(tile_type);
}
const std::vector<PseudoPipBel> &PseudoPipData::get_logic_bels_for_pip(const Context *ctx, int32_t site, PipId pip) const { const std::vector<PseudoPipBel> &PseudoPipData::get_logic_bels_for_pip(const Context *ctx, int32_t site,
PipId pip) const
{
int32_t tile_type = ctx->chip_info->tiles[pip.tile].type; int32_t tile_type = ctx->chip_info->tiles[pip.tile].type;
return logic_bels_for_pip.at(LogicBelKey{tile_type, pip.index, site}); return logic_bels_for_pip.at(LogicBelKey{tile_type, pip.index, site});
} }
void PseudoPipModel::init(Context *ctx, int32_t tile_idx) { void PseudoPipModel::init(Context *ctx, int32_t tile_idx)
{
int32_t tile_type = ctx->chip_info->tiles[tile_idx].type; int32_t tile_type = ctx->chip_info->tiles[tile_idx].type;
this->tile = tile_idx; this->tile = tile_idx;
@ -189,7 +192,8 @@ void PseudoPipModel::init(Context *ctx, int32_t tile_idx) {
allowed_pseudo_pips.fill(true); allowed_pseudo_pips.fill(true);
} }
void PseudoPipModel::prepare_for_routing(const Context *ctx, const std::vector<SiteRouter> & sites) { void PseudoPipModel::prepare_for_routing(const Context *ctx, const std::vector<SiteRouter> &sites)
{
// First determine which sites have placed cells, these sites are consider // First determine which sites have placed cells, these sites are consider
// active. // active.
HashTables::HashSet<size_t> active_sites; HashTables::HashSet<size_t> active_sites;
@ -240,7 +244,8 @@ void PseudoPipModel::prepare_for_routing(const Context *ctx, const std::vector<S
} }
} }
bool PseudoPipModel::checkPipAvail(const Context *ctx, PipId pip) const { bool PseudoPipModel::checkPipAvail(const Context *ctx, PipId pip) const
{
bool allowed = allowed_pseudo_pips.get(pip.index); bool allowed = allowed_pseudo_pips.get(pip.index);
if (!allowed) { if (!allowed) {
#ifdef DEBUG_PSEUDO_PIP #ifdef DEBUG_PSEUDO_PIP
@ -253,7 +258,8 @@ bool PseudoPipModel::checkPipAvail(const Context *ctx, PipId pip) const {
return allowed; return allowed;
} }
void PseudoPipModel::bindPip(const Context *ctx, PipId pip) { void PseudoPipModel::bindPip(const Context *ctx, PipId pip)
{
// If pseudo_pip_sites is empty, then prepare_for_routing was never // If pseudo_pip_sites is empty, then prepare_for_routing was never
// invoked. This is likely because PseudoPipModel was constructed during // invoked. This is likely because PseudoPipModel was constructed during
// routing. // routing.
@ -273,7 +279,8 @@ void PseudoPipModel::bindPip(const Context *ctx, PipId pip) {
update_site(ctx, site); update_site(ctx, site);
} }
void PseudoPipModel::unbindPip(const Context *ctx, PipId pip) { void PseudoPipModel::unbindPip(const Context *ctx, PipId pip)
{
// It should not be possible for unbindPip to be invoked with // It should not be possible for unbindPip to be invoked with
// pseudo_pip_sites being empty. // pseudo_pip_sites being empty.
NPNR_ASSERT(!pseudo_pip_sites.empty()); NPNR_ASSERT(!pseudo_pip_sites.empty());
@ -285,7 +292,8 @@ void PseudoPipModel::unbindPip(const Context *ctx, PipId pip) {
update_site(ctx, site); update_site(ctx, site);
} }
void PseudoPipModel::update_site(const Context *ctx, size_t site) { void PseudoPipModel::update_site(const Context *ctx, size_t site)
{
// update_site consists of several steps: // update_site consists of several steps:
// //
// - Find all BELs within the site used by pseudo pips. // - Find all BELs within the site used by pseudo pips.
@ -404,8 +412,7 @@ void PseudoPipModel::update_site(const Context *ctx, size_t site) {
BelId abel; BelId abel;
abel.tile = tile; abel.tile = tile;
abel.index = bel.bel_index; abel.index = bel.bel_index;
log_info("Pseudo pip %s is block by a bound BEL %s\n", log_info("Pseudo pip %s is block by a bound BEL %s\n", ctx->nameOfPip(pip), ctx->nameOfBel(abel));
ctx->nameOfPip(pip), ctx->nameOfBel(abel));
} }
#endif #endif
break; break;
@ -414,8 +421,7 @@ void PseudoPipModel::update_site(const Context *ctx, size_t site) {
if (used_bels.count(bel.bel_index)) { if (used_bels.count(bel.bel_index)) {
#ifdef DEBUG_PSEUDO_PIP #ifdef DEBUG_PSEUDO_PIP
if (ctx->verbose) { if (ctx->verbose) {
log_info("Pseudo pip %s is block by another pseudo pip\n", log_info("Pseudo pip %s is block by another pseudo pip\n", ctx->nameOfPip(pip));
ctx->nameOfPip(pip));
} }
#endif #endif
blocked_by_bel = true; blocked_by_bel = true;
@ -456,8 +462,7 @@ void PseudoPipModel::update_site(const Context *ctx, size_t site) {
if (blocked_by_lut_eq) { if (blocked_by_lut_eq) {
#ifdef DEBUG_PSEUDO_PIP #ifdef DEBUG_PSEUDO_PIP
if (ctx->verbose) { if (ctx->verbose) {
log_info("Pseudo pip %s is blocked by lut eq\n", log_info("Pseudo pip %s is blocked by lut eq\n", ctx->nameOfPip(pip));
ctx->nameOfPip(pip));
} }
#endif #endif
allowed_pseudo_pips.set(pseudo_pip, false); allowed_pseudo_pips.set(pseudo_pip, false);

31
fpga_interchange/pseudo_pip_model.h
View File

@ -23,15 +23,16 @@
#include <tuple> #include <tuple>
#include "dynamic_bitarray.h"
#include "hash_table.h"
#include "nextpnr_namespaces.h" #include "nextpnr_namespaces.h"
#include "nextpnr_types.h" #include "nextpnr_types.h"
#include "site_router.h" #include "site_router.h"
#include "dynamic_bitarray.h"
#include "hash_table.h"
NEXTPNR_NAMESPACE_BEGIN NEXTPNR_NAMESPACE_BEGIN
struct PseudoPipBel { struct PseudoPipBel
{
// Which BEL in the tile does the pseudo pip use? // Which BEL in the tile does the pseudo pip use?
int32_t bel_index; int32_t bel_index;
@ -46,22 +47,17 @@ struct PseudoPipBel {
int32_t output_bel_pin; int32_t output_bel_pin;
}; };
struct LogicBelKey { struct LogicBelKey
{
int32_t tile_type; int32_t tile_type;
int32_t pip_index; int32_t pip_index;
int32_t site; int32_t site;
std::tuple<int32_t, int32_t, int32_t> make_tuple() const { std::tuple<int32_t, int32_t, int32_t> make_tuple() const { return std::make_tuple(tile_type, pip_index, site); }
return std::make_tuple(tile_type, pip_index, site);
}
bool operator == (const LogicBelKey & other) const { bool operator==(const LogicBelKey &other) const { return make_tuple() == other.make_tuple(); }
return make_tuple() == other.make_tuple();
}
bool operator < (const LogicBelKey & other) const { bool operator<(const LogicBelKey &other) const { return make_tuple() < other.make_tuple(); }
return make_tuple() < other.make_tuple();
}
}; };
NEXTPNR_NAMESPACE_END NEXTPNR_NAMESPACE_END
@ -80,13 +76,13 @@ template <> struct hash<NEXTPNR_NAMESPACE_PREFIX LogicBelKey>
} }
}; };
}; }; // namespace std
NEXTPNR_NAMESPACE_BEGIN NEXTPNR_NAMESPACE_BEGIN
// Storage for tile type generic pseudo pip data and lookup. // Storage for tile type generic pseudo pip data and lookup.
struct PseudoPipData { struct PseudoPipData
{
// Initial data for specified tile type, if not already initialized. // Initial data for specified tile type, if not already initialized.
void init_tile_type(const Context *ctx, int32_t tile_type); void init_tile_type(const Context *ctx, int32_t tile_type);
@ -107,7 +103,8 @@ struct PseudoPipData {
}; };
// Tile instance fast pseudo pip lookup. // Tile instance fast pseudo pip lookup.
struct PseudoPipModel { struct PseudoPipModel
{
int32_t tile; int32_t tile;
DynamicBitarray<> allowed_pseudo_pips; DynamicBitarray<> allowed_pseudo_pips;
HashTables::HashMap<int32_t, size_t> pseudo_pip_sites; HashTables::HashMap<int32_t, size_t> pseudo_pip_sites;

1
fpga_interchange/site_arch.impl.h
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@ -322,7 +322,6 @@ inline SiteWire SiteArch::getBelPinWire(BelId bel, IdString pin) const
inline PortType SiteArch::getBelPinType(BelId bel, IdString pin) const { return ctx->getBelPinType(bel, pin); } inline PortType SiteArch::getBelPinType(BelId bel, IdString pin) const { return ctx->getBelPinType(bel, pin); }
NEXTPNR_NAMESPACE_END NEXTPNR_NAMESPACE_END
#endif /* SITE_ARCH_H */ #endif /* SITE_ARCH_H */

14
fpga_interchange/site_router.cc
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@ -675,7 +675,8 @@ static bool find_solution_via_backtrack(SiteArch *ctx, std::vector<PossibleSolut
NPNR_ASSERT(false); NPNR_ASSERT(false);
} }
static bool route_site(SiteArch *ctx, SiteRoutingCache *site_routing_cache, RouteNodeStorage *node_storage, bool explain) static bool route_site(SiteArch *ctx, SiteRoutingCache *site_routing_cache, RouteNodeStorage *node_storage,
bool explain)
{ {
// Overview: // Overview:
// - Starting from each site net source, expand the site routing graph // - Starting from each site net source, expand the site routing graph
@ -987,7 +988,8 @@ static void apply_routing(Context *ctx, const SiteArch &site_arch)
} }
static bool map_luts_in_site(const SiteInformation &site_info, static bool map_luts_in_site(const SiteInformation &site_info,
HashTables::HashSet<std::pair<IdString, IdString>> *blocked_wires) { HashTables::HashSet<std::pair<IdString, IdString>> *blocked_wires)
{
const Context *ctx = site_info.ctx; const Context *ctx = site_info.ctx;
const std::vector<LutElement> &lut_elements = ctx->lut_elements.at(site_info.tile_type); const std::vector<LutElement> &lut_elements = ctx->lut_elements.at(site_info.tile_type);
std::vector<LutMapper> lut_mappers; std::vector<LutMapper> lut_mappers;
@ -1027,10 +1029,10 @@ static bool map_luts_in_site(const SiteInformation &site_info,
return true; return true;
} }
// Block outputs of unavailable LUTs to prevent site router from using them. // Block outputs of unavailable LUTs to prevent site router from using them.
static void block_lut_outputs(SiteArch *site_arch, static void block_lut_outputs(SiteArch *site_arch,
const HashTables::HashSet<std::pair<IdString, IdString>> &blocked_wires) { const HashTables::HashSet<std::pair<IdString, IdString>> &blocked_wires)
{
const Context *ctx = site_arch->site_info->ctx; const Context *ctx = site_arch->site_info->ctx;
auto &tile_info = ctx->chip_info->tile_types[site_arch->site_info->tile_type]; auto &tile_info = ctx->chip_info->tile_types[site_arch->site_info->tile_type];
for (const auto &bel_pin_pair : blocked_wires) { for (const auto &bel_pin_pair : blocked_wires) {
@ -1039,7 +1041,8 @@ static void block_lut_outputs(SiteArch *site_arch,
int32_t bel_index = -1; int32_t bel_index = -1;
for (int32_t i = 0; i < tile_info.bel_data.ssize(); i++) { for (int32_t i = 0; i < tile_info.bel_data.ssize(); i++) {
if (tile_info.bel_data[i].site == site_arch->site_info->site && tile_info.bel_data[i].name == bel_name.index) { if (tile_info.bel_data[i].site == site_arch->site_info->site &&
tile_info.bel_data[i].name == bel_name.index) {
bel_index = i; bel_index = i;
break; break;
} }
@ -1062,7 +1065,6 @@ bool SiteRouter::checkSiteRouting(const Context *ctx, const TileStatus &tile_sta
// - Ensure that the LUT equation elements in the site are legal // - Ensure that the LUT equation elements in the site are legal
// - Check that the site is routable. // - Check that the site is routable.
// Because site routing checks are expensive, cache them. // Because site routing checks are expensive, cache them.
// SiteRouter::bindBel/unbindBel should correctly invalid the cache by // SiteRouter::bindBel/unbindBel should correctly invalid the cache by
// setting dirty=true. // setting dirty=true.