Improving code style and fixing dummy
Signed-off-by: David Shah <davey1576@gmail.com>
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@ -135,6 +135,7 @@ struct SAState
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bool improved = false;
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bool improved = false;
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int n_move, n_accept;
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int n_move, n_accept;
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int diameter = 35;
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int diameter = 35;
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std::unordered_map<BelType, int> bel_types;
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std::vector<std::vector<std::vector<std::vector<BelId>>>> fast_bels;
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std::vector<std::vector<std::vector<std::vector<BelId>>>> fast_bels;
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std::unordered_set<BelId> locked_bels;
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std::unordered_set<BelId> locked_bels;
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};
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};
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@ -267,7 +268,6 @@ BelId random_bel_for_cell(Design *design, CellInfo *cell, SAState &state,
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BelId best_bel = BelId();
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BelId best_bel = BelId();
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Chip &chip = design->chip;
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Chip &chip = design->chip;
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BelType targetType = belTypeFromId(cell->type);
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BelType targetType = belTypeFromId(cell->type);
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assert(int(targetType) < state.fast_bels.size());
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int x = 0, y = 0;
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int x = 0, y = 0;
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chip.estimatePosition(cell->bel, x, y);
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chip.estimatePosition(cell->bel, x, y);
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while (true) {
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while (true) {
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@ -275,11 +275,12 @@ BelId random_bel_for_cell(Design *design, CellInfo *cell, SAState &state,
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int(x) + state.diameter + 1);
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int(x) + state.diameter + 1);
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int ny = random_int_between(rnd, std::max(int(y) - state.diameter, 0),
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int ny = random_int_between(rnd, std::max(int(y) - state.diameter, 0),
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int(y) + state.diameter + 1);
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int(y) + state.diameter + 1);
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if (nx >= state.fast_bels.at(int(targetType)).size())
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int beltype_idx = state.bel_types.at(targetType);
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if (nx >= state.fast_bels.at(beltype_idx).size())
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continue;
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continue;
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if (ny >= state.fast_bels.at(int(targetType)).at(nx).size())
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if (ny >= state.fast_bels.at(beltype_idx).at(nx).size())
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continue;
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continue;
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const auto &fb = state.fast_bels.at(int(targetType)).at(nx).at(ny);
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const auto &fb = state.fast_bels.at(beltype_idx).at(nx).at(ny);
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if (fb.size() == 0)
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if (fb.size() == 0)
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continue;
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continue;
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BelId bel = fb.at(random_int_between(rnd, 0, fb.size()));
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BelId bel = fb.at(random_int_between(rnd, 0, fb.size()));
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@ -343,19 +344,27 @@ void place_design_sa(Design *design, int seed)
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}
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}
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// Build up a fast position/type to Bel lookup table
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// Build up a fast position/type to Bel lookup table
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int max_x = 0, max_y = 0;
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int max_x = 0, max_y = 0;
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int bel_types = 0;
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for (auto bel : design->chip.getBels()) {
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for (auto bel : design->chip.getBels()) {
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int x, y;
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int x, y;
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design->chip.estimatePosition(bel, x, y);
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design->chip.estimatePosition(bel, x, y);
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BelType type = design->chip.getBelType(bel);
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BelType type = design->chip.getBelType(bel);
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if (state.fast_bels.size() < int(type) + 1)
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int type_idx;
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state.fast_bels.resize(int(type) + 1);
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if (state.bel_types.find(type) == state.bel_types.end()) {
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if (state.fast_bels.at(int(type)).size() < int(x) + 1)
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type_idx = bel_types++;
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state.fast_bels.at(int(type)).resize(int(x) + 1);
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state.bel_types[type] = type_idx;
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if (state.fast_bels.at(int(type)).at(int(x)).size() < int(y) + 1)
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} else {
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state.fast_bels.at(int(type)).at(int(x)).resize(int(y) + 1);
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type_idx = state.bel_types.at(type);
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}
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if (state.fast_bels.size() < type_idx + 1)
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state.fast_bels.resize(type_idx + 1);
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if (state.fast_bels.at(type_idx).size() < int(x) + 1)
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state.fast_bels.at(type_idx).resize(int(x) + 1);
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if (state.fast_bels.at(type_idx).at(int(x)).size() < int(y) + 1)
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state.fast_bels.at(type_idx).at(int(x)).resize(int(y) + 1);
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max_x = std::max(max_x, int(x));
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max_x = std::max(max_x, int(x));
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max_y = std::max(max_y, int(y));
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max_y = std::max(max_y, int(y));
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state.fast_bels.at(int(type)).at(int(x)).at(int((y))).push_back(bel);
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state.fast_bels.at(type_idx).at(int(x)).at(int((y))).push_back(bel);
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}
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}
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state.diameter = std::max(max_x, max_y) + 1;
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state.diameter = std::max(max_x, max_y) + 1;
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// Calculate wirelength after initial placement
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// Calculate wirelength after initial placement
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@ -26,4 +26,9 @@ bool isValidBelForCell(Design *design, CellInfo *cell, BelId bel)
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return true;
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return true;
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}
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}
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bool isBelLocationValid(Design *design, BelId bel)
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{
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return true;
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}
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NEXTPNR_NAMESPACE_END
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NEXTPNR_NAMESPACE_END
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@ -31,6 +31,9 @@ NEXTPNR_NAMESPACE_BEGIN
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// such as conflicting set/reset signals, etc
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// such as conflicting set/reset signals, etc
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bool isValidBelForCell(Design *design, CellInfo *cell, BelId bel);
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bool isValidBelForCell(Design *design, CellInfo *cell, BelId bel);
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// Return true whether all Bels at a given location are valid
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bool isBelLocationValid(Design *design, BelId bel);
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NEXTPNR_NAMESPACE_END
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NEXTPNR_NAMESPACE_END
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#endif
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#endif
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@ -741,9 +741,10 @@ void json_import(Design *design, string modname, JsonNode *node)
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netnames.resize(netid + 1);
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netnames.resize(netid + 1);
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netnames.at(netid) =
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netnames.at(netid) =
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basename +
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basename +
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(num_bits == 1 ? "" : std::string("[") +
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(num_bits == 1
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std::to_string(i) +
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? ""
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std::string("]"));
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: std::string("[") + std::to_string(i) +
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std::string("]"));
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}
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}
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}
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}
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}
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}
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@ -147,7 +147,8 @@ void dff_to_lc(CellInfo *dff, CellInfo *lc, bool pass_thru_lut)
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if (citer != config.end()) {
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if (citer != config.end()) {
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if ((config.end() - citer) >= 2) {
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if ((config.end() - citer) >= 2) {
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assert(*(citer++) == 'S');
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char c = *(citer++);
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assert(c == 'S');
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lc->params["ASYNC_SR"] = "0";
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lc->params["ASYNC_SR"] = "0";
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} else {
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} else {
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lc->params["ASYNC_SR"] = "1";
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lc->params["ASYNC_SR"] = "1";
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