From fcc3bb14959e96073f736050f4085b42589ea9a7 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Wed, 27 Feb 2019 11:57:36 +0000
Subject: [PATCH] ecp5: Speedup cell delay lookups

Signed-off-by: David Shah <dave@ds0.me>
---
 ecp5/arch.cc |  8 +++++++-
 ecp5/arch.h  | 23 +++++++++++++++++++++++
 2 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index 938b5f8e..d4b53f47 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -620,6 +620,11 @@ DecalXY Arch::getGroupDecal(GroupId pip) const { return {}; };
 
 bool Arch::getDelayFromTimingDatabase(IdString tctype, IdString from, IdString to, DelayInfo &delay) const
 {
+    auto fnd_dk = celldelay_cache.find({tctype, from, to});
+    if (fnd_dk != celldelay_cache.end()) {
+        delay = fnd_dk->second.second;
+        return fnd_dk->second.first;
+    }
     for (int i = 0; i < speed_grade->num_cell_timings; i++) {
         const auto &tc = speed_grade->cell_timings[i];
         if (tc.cell_type == tctype.index) {
@@ -628,9 +633,11 @@ bool Arch::getDelayFromTimingDatabase(IdString tctype, IdString from, IdString t
                 if (dly.from_port == from.index && dly.to_port == to.index) {
                     delay.max_delay = dly.max_delay;
                     delay.min_delay = dly.min_delay;
+                    celldelay_cache[{tctype, from, to}] = std::make_pair(true, delay);
                     return true;
                 }
             }
+            celldelay_cache[{tctype, from, to}] = std::make_pair(false, DelayInfo());
             return false;
         }
     }
@@ -660,7 +667,6 @@ void Arch::getSetupHoldFromTimingDatabase(IdString tctype, IdString clock, IdStr
 
 bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
 {
-
     // Data for -8 grade
     if (cell->type == id_TRELLIS_SLICE) {
         bool has_carry = cell->sliceInfo.is_carry;
diff --git a/ecp5/arch.h b/ecp5/arch.h
index ab4a4e00..b19e008f 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -448,6 +448,27 @@ struct ArchArgs
     } speed = SPEED_6;
 };
 
+struct DelayKey {
+    IdString celltype, from, to;
+    inline bool operator==(const DelayKey &other) const {
+        return celltype == other.celltype && from == other.from && to == other.to;
+    }
+};
+
+NEXTPNR_NAMESPACE_END
+namespace std {
+    template<>
+    struct hash<NEXTPNR_NAMESPACE_PREFIX DelayKey> {
+        std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX DelayKey &dk) const noexcept {
+            std::size_t seed = std::hash<NEXTPNR_NAMESPACE_PREFIX IdString>()(dk.celltype);
+            seed ^= std::hash<NEXTPNR_NAMESPACE_PREFIX IdString>()(dk.from) + 0x9e3779b9 + (seed << 6) + (seed >> 2);
+            seed ^= std::hash<NEXTPNR_NAMESPACE_PREFIX IdString>()(dk.to) + 0x9e3779b9 + (seed << 6) + (seed >> 2);
+            return seed;
+        }
+    };
+}
+NEXTPNR_NAMESPACE_BEGIN
+
 struct Arch : BaseCtx
 {
     const ChipInfoPOD *chip_info;
@@ -1019,6 +1040,8 @@ struct Arch : BaseCtx
     IdString id_clk, id_lsr;
     IdString id_clkmux, id_lsrmux;
     IdString id_srmode, id_mode;
+
+    mutable std::unordered_map<DelayKey, std::pair<bool, DelayInfo>> celldelay_cache;
 };
 
 NEXTPNR_NAMESPACE_END