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ecp5: Fix how ODDRX2 SCLK/RST are set

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Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2020-08-13 13:24:52 +01:00
parent fbe486df45
commit fd5d95320b
1 changed files with 8 additions and 8 deletions
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16
ecp5/pack.cc
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@ -1992,7 +1992,7 @@ class Ecp5Packer
{ {
std::unordered_map<IdString, CellInfo *> pio_iologic; std::unordered_map<IdString, CellInfo *> pio_iologic;
auto set_iologic_sclk = [&](CellInfo *iol, CellInfo *prim, IdString port, bool input) { auto set_iologic_sclk = [&](CellInfo *iol, CellInfo *prim, IdString port, bool input, bool disconnect = true) {
NetInfo *sclk = nullptr; NetInfo *sclk = nullptr;
if (prim->ports.count(port)) if (prim->ports.count(port))
sclk = prim->ports[port].net; sclk = prim->ports[port].net;
@ -2008,7 +2008,7 @@ class Ecp5Packer
connect_port(ctx, sclk, iol, id_CLK); connect_port(ctx, sclk, iol, id_CLK);
} }
} }
if (prim->ports.count(port)) if (prim->ports.count(port) && disconnect)
disconnect_port(ctx, prim, port); disconnect_port(ctx, prim, port);
}; };
@ -2030,7 +2030,7 @@ class Ecp5Packer
disconnect_port(ctx, prim, port); disconnect_port(ctx, prim, port);
}; };
auto set_iologic_lsr = [&](CellInfo *iol, CellInfo *prim, IdString port, bool input) { auto set_iologic_lsr = [&](CellInfo *iol, CellInfo *prim, IdString port, bool input, bool disconnect = true) {
NetInfo *lsr = nullptr; NetInfo *lsr = nullptr;
if (prim->ports.count(port)) if (prim->ports.count(port))
lsr = prim->ports[port].net; lsr = prim->ports[port].net;
@ -2046,7 +2046,7 @@ class Ecp5Packer
connect_port(ctx, lsr, iol, id_LSR); connect_port(ctx, lsr, iol, id_LSR);
} }
} }
if (prim->ports.count(port)) if (prim->ports.count(port) && disconnect)
disconnect_port(ctx, prim, port); disconnect_port(ctx, prim, port);
}; };
@ -2282,10 +2282,10 @@ class Ecp5Packer
pio->ports[id_IOLDO].type = PORT_IN; pio->ports[id_IOLDO].type = PORT_IN;
} }
replace_port(pio, id_I, pio, id_IOLDO); replace_port(pio, id_I, pio, id_IOLDO);
set_iologic_sclk(iol, ci, ctx->id("SCLK"), false); set_iologic_sclk(iol, ci, ctx->id("SCLK"), false, false);
set_iologic_sclk(iol, ci, ctx->id("SCLK"), true); set_iologic_sclk(iol, ci, ctx->id("SCLK"), true);
set_iologic_eclk(iol, ci, id_ECLK); set_iologic_eclk(iol, ci, id_ECLK);
set_iologic_lsr(iol, ci, ctx->id("RST"), false); set_iologic_lsr(iol, ci, ctx->id("RST"), false, false);
set_iologic_lsr(iol, ci, ctx->id("RST"), true); set_iologic_lsr(iol, ci, ctx->id("RST"), true);
replace_port(ci, ctx->id("D0"), iol, id_TXDATA0); replace_port(ci, ctx->id("D0"), iol, id_TXDATA0);
replace_port(ci, ctx->id("D1"), iol, id_TXDATA1); replace_port(ci, ctx->id("D1"), iol, id_TXDATA1);
@ -2359,7 +2359,7 @@ class Ecp5Packer
replace_port(pio, id_I, pio, id_IOLDO); replace_port(pio, id_I, pio, id_IOLDO);
set_iologic_sclk(iol, ci, ctx->id("SCLK"), false); set_iologic_sclk(iol, ci, ctx->id("SCLK"), false);
set_iologic_eclk(iol, ci, id_ECLK); set_iologic_eclk(iol, ci, id_ECLK);
set_iologic_lsr(iol, ci, ctx->id("RST"), false); set_iologic_lsr(iol, ci, ctx->id("RST"), false, false);
set_iologic_lsr(iol, ci, ctx->id("RST"), true); set_iologic_lsr(iol, ci, ctx->id("RST"), true);
replace_port(ci, ctx->id("D0"), iol, id_TXDATA0); replace_port(ci, ctx->id("D0"), iol, id_TXDATA0);
replace_port(ci, ctx->id("D1"), iol, id_TXDATA2); replace_port(ci, ctx->id("D1"), iol, id_TXDATA2);
@ -2386,7 +2386,7 @@ class Ecp5Packer
replace_port(pio, id_I, pio, id_IOLDO); replace_port(pio, id_I, pio, id_IOLDO);
set_iologic_sclk(iol, ci, ctx->id("SCLK"), false); set_iologic_sclk(iol, ci, ctx->id("SCLK"), false);
set_iologic_eclk(iol, ci, id_ECLK); set_iologic_eclk(iol, ci, id_ECLK);
set_iologic_lsr(iol, ci, ctx->id("RST"), false); set_iologic_lsr(iol, ci, ctx->id("RST"), false, false);
set_iologic_lsr(iol, ci, ctx->id("RST"), true); set_iologic_lsr(iol, ci, ctx->id("RST"), true);
replace_port(ci, ctx->id("D0"), iol, id_TXDATA0); replace_port(ci, ctx->id("D0"), iol, id_TXDATA0);
replace_port(ci, ctx->id("D1"), iol, id_TXDATA1); replace_port(ci, ctx->id("D1"), iol, id_TXDATA1);