diff --git a/himbaechel/uarch/gatemate/bitstream.cc b/himbaechel/uarch/gatemate/bitstream.cc
index 4d21ea65..77137715 100644
--- a/himbaechel/uarch/gatemate/bitstream.cc
+++ b/himbaechel/uarch/gatemate/bitstream.cc
@@ -133,6 +133,10 @@ struct BitstreamBackend
                 }
             } break;
             case id_BUFG.index:
+                {
+                    Loc l = ctx->getBelLocation(cell.second->bel);
+                    cc.configs[0].add_word(stringf("GLBOUT.GLB%d_EN",l.z), int_to_bitvector(1,1));
+                }
             break;
             default:
                 log_error("Unhandled cell %s of type %s\n", cell.second.get()->name.c_str(ctx),
diff --git a/himbaechel/uarch/gatemate/gatemate.cc b/himbaechel/uarch/gatemate/gatemate.cc
index d69a864e..847c72f9 100644
--- a/himbaechel/uarch/gatemate/gatemate.cc
+++ b/himbaechel/uarch/gatemate/gatemate.cc
@@ -118,6 +118,17 @@ void GateMateImpl::postRoute()
                             cell->params[id_INIT_L20] = Property(0b1100, 4);
                             cell->params[id_O2] = Property(0b11, 2);
                             cell->params[id_RAM_O2] = Property(1, 1);
+                        } else if (IdString(extra_data.name) == id_RAM_O1) {
+                            cell->params[id_INIT_L00] = Property(0b1010, 4);
+                            cell->params[id_INIT_L01] = Property(0b1111, 4);
+                            cell->params[id_INIT_L02] = Property(0b1111, 4);
+                            cell->params[id_INIT_L03] = Property(0b1111, 4);
+                            cell->params[id_INIT_L10] = Property(0b1000, 4);
+                            cell->params[id_INIT_L20] = Property(0b1010, 4);
+                            cell->params[id_O1] = Property(0b11, 2);
+                            cell->params[id_RAM_O1] = Property(1, 1);
+                        } else {
+                            log_error("Issue adding pass trough signal for %s.\n",IdString(extra_data.name).c_str(ctx));
                         }
                     } else
                         log_error("Issue adding pass trough signal.\n");
diff --git a/himbaechel/uarch/gatemate/gen/arch_gen.py b/himbaechel/uarch/gatemate/gen/arch_gen.py
index 1b2a8620..1e526679 100644
--- a/himbaechel/uarch/gatemate/gen/arch_gen.py
+++ b/himbaechel/uarch/gatemate/gen/arch_gen.py
@@ -92,6 +92,8 @@ def main():
         if "CPE" in type_name:
             pp = tt.create_pip("CPE.IN1", "CPE.RAM_O2")
             pp.extra_data = PipExtraData(PIP_EXTRA_CPE,ch.strs.id("RAM_O2"))
+            pp = tt.create_pip("CPE.IN1", "CPE.RAM_O1")
+            pp.extra_data = PipExtraData(PIP_EXTRA_CPE,ch.strs.id("RAM_O1"))
             for i in range(1,9):
                 tt.create_wire(f"CPE.V_IN{i}", "CPE_VIRTUAL_WIRE")
                 pp = tt.create_pip(f"CPE.V_IN{i}", f"CPE.IN{i}")