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BUFG support

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This commit is contained in:
Miodrag Milanovic 2025-01-13 13:16:58 +01:00
parent 2a41124378
commit fdb2dd4c42
3 changed files with 17 additions and 0 deletions
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4
himbaechel/uarch/gatemate/bitstream.cc
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@ -133,6 +133,10 @@ struct BitstreamBackend
} }
} break; } break;
case id_BUFG.index: case id_BUFG.index:
{
Loc l = ctx->getBelLocation(cell.second->bel);
cc.configs[0].add_word(stringf("GLBOUT.GLB%d_EN",l.z), int_to_bitvector(1,1));
}
break; break;
default: default:
log_error("Unhandled cell %s of type %s\n", cell.second.get()->name.c_str(ctx), log_error("Unhandled cell %s of type %s\n", cell.second.get()->name.c_str(ctx),

11
himbaechel/uarch/gatemate/gatemate.cc
View File

@ -118,6 +118,17 @@ void GateMateImpl::postRoute()
cell->params[id_INIT_L20] = Property(0b1100, 4); cell->params[id_INIT_L20] = Property(0b1100, 4);
cell->params[id_O2] = Property(0b11, 2); cell->params[id_O2] = Property(0b11, 2);
cell->params[id_RAM_O2] = Property(1, 1); cell->params[id_RAM_O2] = Property(1, 1);
} else if (IdString(extra_data.name) == id_RAM_O1) {
cell->params[id_INIT_L00] = Property(0b1010, 4);
cell->params[id_INIT_L01] = Property(0b1111, 4);
cell->params[id_INIT_L02] = Property(0b1111, 4);
cell->params[id_INIT_L03] = Property(0b1111, 4);
cell->params[id_INIT_L10] = Property(0b1000, 4);
cell->params[id_INIT_L20] = Property(0b1010, 4);
cell->params[id_O1] = Property(0b11, 2);
cell->params[id_RAM_O1] = Property(1, 1);
} else {
log_error("Issue adding pass trough signal for %s.\n",IdString(extra_data.name).c_str(ctx));
} }
} else } else
log_error("Issue adding pass trough signal.\n"); log_error("Issue adding pass trough signal.\n");

2
himbaechel/uarch/gatemate/gen/arch_gen.py
View File

@ -92,6 +92,8 @@ def main():
if "CPE" in type_name: if "CPE" in type_name:
pp = tt.create_pip("CPE.IN1", "CPE.RAM_O2") pp = tt.create_pip("CPE.IN1", "CPE.RAM_O2")
pp.extra_data = PipExtraData(PIP_EXTRA_CPE,ch.strs.id("RAM_O2")) pp.extra_data = PipExtraData(PIP_EXTRA_CPE,ch.strs.id("RAM_O2"))
pp = tt.create_pip("CPE.IN1", "CPE.RAM_O1")
pp.extra_data = PipExtraData(PIP_EXTRA_CPE,ch.strs.id("RAM_O1"))
for i in range(1,9): for i in range(1,9):
tt.create_wire(f"CPE.V_IN{i}", "CPE_VIRTUAL_WIRE") tt.create_wire(f"CPE.V_IN{i}", "CPE_VIRTUAL_WIRE")
pp = tt.create_pip(f"CPE.V_IN{i}", f"CPE.IN{i}") pp = tt.create_pip(f"CPE.V_IN{i}", f"CPE.IN{i}")