Preserve hierarchy through packing
Signed-off-by: David Shah <dave@ds0.me>
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b100087024
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fe40094216
@ -21,6 +21,7 @@
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#include <boost/algorithm/string.hpp>
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#include "design_utils.h"
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#include "log.h"
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#include "util.h"
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NEXTPNR_NAMESPACE_BEGIN
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@ -723,4 +724,76 @@ void BaseCtx::copyBelPorts(IdString cell, BelId bel)
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}
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}
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namespace {
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struct FixupHierarchyWorker
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{
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FixupHierarchyWorker(Context *ctx) : ctx(ctx){};
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Context *ctx;
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void run()
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{
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trim_hierarchy(ctx->top_module);
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rebuild_hierarchy();
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};
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// Remove cells and nets that no longer exist in the netlist
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std::vector<IdString> todelete_cells, todelete_nets;
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void trim_hierarchy(IdString path)
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{
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auto &h = ctx->hierarchy.at(path);
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todelete_cells.clear();
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todelete_nets.clear();
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for (auto &lc : h.leaf_cells) {
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if (!ctx->cells.count(lc.second))
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todelete_cells.push_back(lc.first);
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}
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for (auto &n : h.nets)
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if (!ctx->nets.count(n.second))
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todelete_nets.push_back(n.first);
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for (auto tdc : todelete_cells) {
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h.leaf_cells_by_gname.erase(h.leaf_cells.at(tdc));
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h.leaf_cells.erase(tdc);
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}
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for (auto tdn : todelete_nets) {
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h.nets_by_gname.erase(h.nets.at(tdn));
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h.nets.erase(tdn);
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}
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for (auto &sc : h.hier_cells)
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trim_hierarchy(sc.second);
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}
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IdString construct_local_name(HierarchicalCell &hc, IdString global_name, bool is_cell)
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{
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std::string gn = global_name.str(ctx);
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auto dp = gn.find_last_of('.');
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if (dp != std::string::npos)
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gn = gn.substr(dp + 1);
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IdString name = ctx->id(gn);
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// Make sure name is unique
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int adder = 0;
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while (is_cell ? hc.leaf_cells.count(name) : hc.nets.count(name)) {
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++adder;
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name = ctx->id(gn + "$" + std::to_string(adder));
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}
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return name;
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}
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// Update hierarchy structure for nets and cells that have hiercell set
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void rebuild_hierarchy()
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{
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for (auto cell : sorted(ctx->cells)) {
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CellInfo *ci = cell.second;
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if (ci->hierpath == IdString())
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ci->hierpath = ctx->top_module;
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auto &hc = ctx->hierarchy.at(ci->hierpath);
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if (hc.leaf_cells_by_gname.count(ci->name))
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continue; // already known
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IdString local_name = construct_local_name(hc, ci->name, true);
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hc.leaf_cells_by_gname[ci->name] = local_name;
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hc.leaf_cells[local_name] = ci->name;
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}
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}
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};
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} // namespace
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void Context::fixupHierarchy() { FixupHierarchyWorker(this).run(); }
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NEXTPNR_NAMESPACE_END
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@ -544,6 +544,9 @@ struct HierarchicalCell
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IdString name, type, parent, fullpath;
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// Name inside cell instance -> global name
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std::unordered_map<IdString, IdString> leaf_cells, nets;
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// Global name -> name inside cell instance
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std::unordered_map<IdString, IdString> leaf_cells_by_gname, nets_by_gname;
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// Cell port to net
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std::unordered_map<IdString, HierarchicalPort> ports;
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// Name inside cell instance -> global name
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std::unordered_map<IdString, IdString> hier_cells;
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@ -835,6 +838,10 @@ struct Context : Arch, DeterministicRNG
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bool getActualRouteDelay(WireId src_wire, WireId dst_wire, delay_t *delay = nullptr,
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std::unordered_map<WireId, PipId> *route = nullptr, bool useEstimate = true);
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// --------------------------------------------------------------
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// call after changing hierpath or adding/removing nets and cells
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void fixupHierarchy();
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// --------------------------------------------------------------
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// provided by sdf.cc
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@ -233,6 +233,8 @@ static void replace_port_safe(bool has_ff, CellInfo *ff, IdString ff_port, CellI
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void ff_to_slice(Context *ctx, CellInfo *ff, CellInfo *lc, int index, bool driven_by_lut)
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{
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if (lc->hierpath == IdString())
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lc->hierpath = ff->hierpath;
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bool has_ff = lc->ports.at(ctx->id("Q0")).net != nullptr || lc->ports.at(ctx->id("Q1")).net != nullptr;
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std::string reg = "REG" + std::to_string(index);
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set_param_safe(has_ff, lc, ctx->id("SRMODE"), str_or_default(ff->params, ctx->id("SRMODE"), "LSR_OVER_CE"));
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@ -271,6 +273,8 @@ void ff_to_slice(Context *ctx, CellInfo *ff, CellInfo *lc, int index, bool drive
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void lut_to_slice(Context *ctx, CellInfo *lut, CellInfo *lc, int index)
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{
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if (lc->hierpath == IdString())
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lc->hierpath = lut->hierpath;
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lc->params[ctx->id("LUT" + std::to_string(index) + "_INITVAL")] =
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get_or_default(lut->params, ctx->id("INIT"), Property(0, 16));
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replace_port(lut, ctx->id("A"), lc, ctx->id("A" + std::to_string(index)));
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@ -282,6 +286,8 @@ void lut_to_slice(Context *ctx, CellInfo *lut, CellInfo *lc, int index)
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void ccu2c_to_slice(Context *ctx, CellInfo *ccu, CellInfo *lc)
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{
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if (lc->hierpath == IdString())
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lc->hierpath = ccu->hierpath;
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lc->params[ctx->id("MODE")] = std::string("CCU2");
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lc->params[ctx->id("LUT0_INITVAL")] = get_or_default(ccu->params, ctx->id("INIT0"), Property(0, 16));
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lc->params[ctx->id("LUT1_INITVAL")] = get_or_default(ccu->params, ctx->id("INIT1"), Property(0, 16));
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@ -309,6 +315,8 @@ void ccu2c_to_slice(Context *ctx, CellInfo *ccu, CellInfo *lc)
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void dram_to_ramw(Context *ctx, CellInfo *ram, CellInfo *lc)
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{
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if (lc->hierpath == IdString())
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lc->hierpath = ram->hierpath;
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lc->params[ctx->id("MODE")] = std::string("RAMW");
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replace_port(ram, ctx->id("WAD[0]"), lc, ctx->id("D0"));
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replace_port(ram, ctx->id("WAD[1]"), lc, ctx->id("B0"));
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@ -340,6 +348,8 @@ static unsigned get_dram_init(const Context *ctx, const CellInfo *ram, int bit)
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void dram_to_ram_slice(Context *ctx, CellInfo *ram, CellInfo *lc, CellInfo *ramw, int index)
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{
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if (lc->hierpath == IdString())
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lc->hierpath = ram->hierpath;
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lc->params[ctx->id("MODE")] = std::string("DPRAM");
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lc->params[ctx->id("WREMUX")] = str_or_default(ram->params, ctx->id("WREMUX"), "WRE");
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lc->params[ctx->id("WCKMUX")] = str_or_default(ram->params, ctx->id("WCKMUX"), "WCK");
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@ -423,8 +423,10 @@ template <typename FrontendType> struct GenericFrontend
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void import_leaf_cell(HierModuleState &m, const std::string &name, const cell_dat_t &cd)
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{
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IdString inst_name = unique_name(m.prefix, name, false);
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ctx->hierarchy[m.path].leaf_cells_by_gname[inst_name] = ctx->id(name);
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ctx->hierarchy[m.path].leaf_cells[ctx->id(name)] = inst_name;
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CellInfo *ci = ctx->createCell(inst_name, ctx->id(impl.get_cell_type(cd)));
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ci->hierpath = m.path;
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// Import port directions
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std::unordered_map<IdString, PortType> port_dirs;
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impl.foreach_port_dir(cd, [&](const std::string &port, PortType dir) { port_dirs[ctx->id(port)] = dir; });
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@ -346,6 +346,8 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri
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void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff)
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{
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if (lc->hierpath == IdString())
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lc->hierpath = lut->hierpath;
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lc->params[ctx->id("LUT_INIT")] = lut->params[ctx->id("LUT_INIT")].extract(0, 16, Property::State::S0);
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replace_port(lut, ctx->id("I0"), lc, ctx->id("I0"));
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replace_port(lut, ctx->id("I1"), lc, ctx->id("I1"));
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@ -359,6 +361,8 @@ void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff)
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void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_lut)
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{
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if (lc->hierpath == IdString())
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lc->hierpath = dff->hierpath;
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lc->params[ctx->id("DFF_ENABLE")] = Property::State::S1;
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std::string config = dff->type.str(ctx).substr(6);
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auto citer = config.begin();
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@ -1487,6 +1487,7 @@ bool Arch::pack()
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promote_globals(ctx);
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ctx->assignArchInfo();
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constrain_chains(ctx);
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ctx->fixupHierarchy();
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ctx->assignArchInfo();
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ctx->settings[ctx->id("pack")] = 1;
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archInfoToAttributes();
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