From fe5a7bda440b27a9b23b5ef4b14f44e431296d37 Mon Sep 17 00:00:00 2001 From: YRabbit Date: Fri, 6 Sep 2024 05:47:56 +1000 Subject: [PATCH] Gowin. BUGFIX. Create all Clock Pips. Some Clocks PIPS were not created due to a check for the presence of a delay class, now all wires are attributed to the class so that there is no longer any need for this check. Signed-off-by: YRabbit --- himbaechel/uarch/gowin/gowin_arch_gen.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py index 5457fc62..425d9171 100644 --- a/himbaechel/uarch/gowin/gowin_arch_gen.py +++ b/himbaechel/uarch/gowin/gowin_arch_gen.py @@ -365,8 +365,7 @@ def create_switch_matrix(tt: TileType, db: chipdb, x: int, y: int): if not tt.has_wire(src): tt.create_wire(src, "GLOBAL_CLK") src_tm_class = get_tm_class(db, src) - if src_tm_class in {'CENT_SPINE_PCLK', 'SPINE_TAP_PCLK', 'TAP_BRANCH_PCLK', 'BRANCH_PCLK'}: - tt.create_pip(src, dst, src_tm_class) + tt.create_pip(src, dst, src_tm_class) def create_hclk_switch_matrix(tt: TileType, db: chipdb, x: int, y: int): if (y, x) not in db.hclk_pips: