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213 Commits

Author SHA1 Message Date
gatecat
579b98c596 Use hashlib for core netlist structures 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 14:27:56 +01:00
gatecat
0d6be6f474 Add stub cluster API impl for remaining arches 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 13:12:52 +01:00
Keith Rothman
e7d81913a4 Add "checkPipAvailForNet" to Arch API. 
This is important for distiguishing valid pseudo pips in the FPGA
interchange arch. This also avoids a double or triple lookup of
pip->net map.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-22 09:17:55 -07:00
Keith Rothman
fe4608386e Split nextpnr.h to allow for linear inclusion. 
"nextpnr.h" is no longer the god header.  Important improvements:

 - Functions in log.h can be used without including
   BaseCtx/Arch/Context. This means that log_X functions can be called
   without included "nextpnr.h"

 - NPNR_ASSERT can be used without including "nextpnr.h" by including
   "nextpnr_assertions.h".  This allows NPNR_ASSERT to be used safely in
   any header file.

 - Types defined in "archdefs.h" are now available without including
   BaseCtx/Arch/Context.  This means that utility classes that will be
   used inside of BaseCtx/Arch/Context can be defined safely in a
   self-contained header.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-15 09:05:23 -07:00
Keith Rothman
423a10bc31 Change CellInfo in getBelPinsForCellPin to be const. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:08:54 -08:00
gatecat
7922b3bfc4 Replace DelayInfo with DelayPair/DelayQuad 
This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.

This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.

While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-19 11:31:33 +00:00
gatecat
6b4bd0993f generic: Don't generate Vcc if not needed 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-17 10:24:06 +00:00
gatecat
c7c13cd95f Remove isValidBelForCell 
This Arch API dates from when we were first working out how to
implement placement validity checking, and in practice is little used by
the core parts of placer1/HeAP and the Arch implementation involves a
lot of duplication with isBelLocationValid.

In the short term; placement validity checking is better served by the
combination of checkBelAvail and isValidBelForCellType before placement;
followed by isBelLocationValid after placement (potentially after
moving/swapping multiple cells).

Longer term, removing this API makes things a bit cleaner for a new
validity checking API.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-16 13:31:36 +00:00
gatecat
a002ccfbc1 generic: Add APIs for controlling cell->bel pin mapping 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-15 09:58:56 +00:00
gatecat
1b6cdce925
Merge pull request #575 from YosysHQ/gatecat/belpin-2 
Support for cell pin to bel pin mappings
 2021-02-15 09:38:22 +00:00
Keith Rothman
99e397000c Add getBelHidden and add some missing "override" statements. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-11 14:58:02 -08:00
gatecat
85bb108ba4 Add getBelPinsForCellPin to Arch API 
This is a basic implementation, without considering "M of N"
arrangements (e.g. for LUT permuation where you only want to route to 1
out of 4/6 sinks) or using a type other than IdString to identify bel
pins.

But this is also enough to start working out where in nextpnr will break
due to removing the 1:1 cell:bel pin cardinality, as a next step.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-10 11:54:54 +00:00
D. Shah
efca63862c Use 'T' postfix to disambiguate LHS and RHS of using 
Arches might otherwise have range types named ambigiously with the entry
in ArchRanges.

Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-08 10:29:50 +00:00
D. Shah
3e631fe2f4 Add archArgs and archArgsToId to Arch API 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-05 19:19:17 +00:00
D. Shah
c7ef7e1902 generic: Base upon ArchAPI 
As generic is often picked as our 'odd-one-out' we also use it as an
example of an Arch that does not build upon BaseArch.

Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-05 19:19:17 +00:00
D. Shah
450bfae86c generic: Fix pin names accidentally being IdStringList not IdString 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-05 10:43:35 +00:00
Keith Rothman
c99fbde0eb Mark IdString and IdStringList single argument constructors explicit. 
Single argument constructors will silently convert to that type.  This
is typically not the right thing to do.  For example, the nexus and
ice40 arch_pybindings.h files were incorrectly parsing bel name strings,
etc.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-04 16:38:07 -08:00
D. Shah
15bf9e4f74 Post-rebase fix 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-02 17:07:44 +00:00
D. Shah
7cff69f945 generic: Use IdStringList for all arch object names 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-02 17:00:56 +00:00
D. Shah
ff92d19fed arch: Add getNameDelimiter API for string lists 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-02 16:59:40 +00:00
Keith Rothman
da74a425d2 Run "make clangformat". 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-02 07:44:49 -08:00
Keith Rothman
9089ee2d16 Add pybindings for new APIs. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-02 07:43:36 -08:00
Keith Rothman
9fe546f279 Rename Partition -> BelBucket. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-02 07:34:56 -08:00
Keith Rothman
310f9f7b84 Finish implementing new generic APIs. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-02 07:34:56 -08:00
Keith Rothman
b4160c228e Add archcheck for partition methods. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-02 07:34:56 -08:00
Keith Rothman
2285c8dbbd Initial refactoring of placer API. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-02 07:34:56 -08:00
David Shah
b18ea204c2 Remove wire alias API 
It has not actually been implemented in any router for over 2.5 years and causes nothing more than confusion. It can always be added back if it forms part of a future solution; possibly as part of a more general database structure rethink.

Signed-off-by: David Shah <dave@ds0.me>
 2020-10-15 09:36:15 +01:00
Pepijn de Vos
26dfe6f23d
Update generic synth script for dfflegalize changes 2020-09-18 15:39:24 +02:00
Miodrag Milanovic
fe398ab983 clangformat 2020-07-25 10:17:13 +02:00
Miodrag Milanovic
770bb40eb3 proper argument propagation 2020-07-24 10:47:10 +02:00
Miodrag Milanovic
8f2b707d02 Initial conversion to pybind11 2020-07-23 18:35:18 +02:00
Nathaniel Graff
08f68518f2 Fix spelling of 'unsupported' 
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
 2020-05-13 20:00:37 -07:00
David Shah
1ceffbe0bc
Merge pull request #391 from YosysHQ/router2-upstream 
Upstreaming router2
 2020-02-04 16:08:08 +00:00
David Shah
b4d029a55c
Merge pull request #385 from YosysHQ/router1-arc-fixes 
Fixes for partial reconfig demo
 2020-02-03 13:55:07 +00:00
David Shah
a1c902dadc generic: Implement getRouteBoundingBox 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-03 13:48:51 +00:00
David Shah
2248e07b66 router2: Improve flow and log output 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-03 13:46:05 +00:00
David Shah
7123209324 Allow selection of router algorithm 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-03 11:54:38 +00:00
David Shah
f1dbb0c4f2 Fix latent bug in generic out-of-context IO mode 
Signed-off-by: David Shah <dave@ds0.me>
 2020-01-21 19:06:46 +00:00
David Shah
4754ab3894 clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2020-01-20 20:30:43 +00:00
Miodrag Milanovic
38e3b6338c Various warning fixes 2020-01-18 15:23:35 +01:00
David Shah
b100087024 python: Add bindings for hierarchy structures 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-27 10:44:30 +00:00
David Shah
be37a39ecb generic: Fix width of 0-driver INIT 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-01 17:19:52 +00:00
David Shah
f57c2bcebb generic: Don't assume unused LUT inputs are zero 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-01 17:07:36 +00:00
David Shah
2f56b98959 generic: Add support for post-PnR simulation 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-27 15:17:53 +00:00
David Shah
2b3dda7535 generic: Add support for disabling IOB insertion 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-27 14:42:05 +00:00
David Shah
2957eb7cc9 generic: Improve error handling when Wire/Pip/Bel is not found 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-27 14:33:35 +00:00
David Shah
defafcf5fe generic: Use HeAP as placer where possible 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-26 10:10:26 +00:00
David Shah
0a8e9b0fbd clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-18 15:07:55 +00:00
Pepijn de Vos
ea05c48032 leftover Q from before slice api change 2019-11-18 10:48:19 +01:00
Pepijn de Vos
a4848f6902 more formatting 2019-11-08 17:18:50 +01:00
Pepijn de Vos
5dd1e5e51e return FF_USED, formatting, correct INIT 2019-11-08 17:15:12 +01:00
Pepijn de Vos
7c362f292c dedicated output for LUT in GENERIC_SLICE 2019-11-08 15:54:27 +01:00
David Shah
ebcdfc1ae8 generic: New Property interface 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-05 17:28:54 +01:00
Miodrag Milanovic
be47fc3e9a clangformat run 2019-06-25 18:19:25 +02:00
Miodrag Milanovic
66ea9f39f7 enable lading of jsons and setting up context 2019-06-14 15:18:35 +02:00
Miodrag Milanovic
36ccc22fc9 Use flags for each step 2019-06-14 09:59:04 +02:00
Miodrag Milanovic
ca7e944d7a restore arch info for ecp5 2019-06-14 08:55:11 +02:00
Miodrag Milanovic
03dff10cbd Load properties from json and propagate to context create 2019-06-13 20:42:11 +02:00
Miodrag Milanovic
1cd4a4d17a Remove concept of project and code connected 2019-06-13 17:42:41 +02:00
Miodrag Milanovic
d9b0bac248 Save top level attrs and store current step 2019-06-07 16:11:11 +02:00
Miodrag Milanovic
78e6631f76 Cleanup 2019-06-07 13:49:19 +02:00
Miodrag Milanovic
1093d7e122 WIP saving/loading attributes 2019-06-07 11:48:15 +02:00
David Shah
c33da42365 ci: Run generic example simple.sh 
Signed-off-by: David Shah <dave@ds0.me>
 2019-04-17 13:02:01 +01:00
David Shah
9fa13b5adc pybindings: make errors in Python scripts stop nextpnr execution 
Signed-off-by: David Shah <dave@ds0.me>
 2019-04-17 11:12:58 +01:00
David Shah
48c4c1ed05 generic/examples: Add FASM writer Python script 
Signed-off-by: David Shah <dave@ds0.me>
 2019-04-17 11:00:23 +01:00
David Shah
659c932559 generic: Fix predictDelay 
Signed-off-by: David Shah <dave@ds0.me>
 2019-04-04 16:58:43 +01:00
David Shah
f12a209391 generic: Router param tweaks 
Signed-off-by: David Shah <dave@ds0.me>
 2019-04-04 16:46:05 +01:00
David Shah
f0cd51e6bc generic: Cell timing support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-04-04 16:34:06 +01:00
David Shah
3f98084021 generic: Improve example 
Signed-off-by: David Shah <dave@ds0.me>
 2019-04-04 15:40:48 +01:00
David Shah
6fffe24177 generic: GUI Python bindings 
Signed-off-by: David Shah <dave@ds0.me>
 2019-04-03 16:08:33 +01:00
David Shah
a05593da62 generic: Add a few more bindings 
Signed-off-by: David Shah <dave@ds0.me>
 2019-04-02 15:30:01 +01:00
David Shah
32327b761a generic: Simple working example 
Signed-off-by: David Shah <dave@ds0.me>
 2019-04-02 15:30:01 +01:00
David Shah
6a383cd4c5 generic: Simple procedural example works 
Signed-off-by: David Shah <dave@ds0.me>
 2019-04-02 15:30:01 +01:00
David Shah
ca918078bf generic: Add a simple packer for generic SLICEs and IOBs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-04-02 15:30:01 +01:00
David Shah
99c3713293 generic: Add synth_generic.tcl 
Signed-off-by: David Shah <dave@ds0.me>
 2019-04-02 15:30:01 +01:00
David Shah
f88ddf85b2 generic: Add simple primitive library 
Signed-off-by: David Shah <dave@ds0.me>
 2019-04-02 15:30:01 +01:00
David Shah
50fd8aa01f generic: Place a single SLICE 
Signed-off-by: David Shah <dave@ds0.me>
 2019-04-02 15:30:01 +01:00
David Shah
fd3ad75598 generic: Python bindings for arch construction 
Signed-off-by: David Shah <dave@ds0.me>
 2019-04-02 15:30:01 +01:00
David Shah
30f0c582e4 python: Named argument support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-04-02 15:30:01 +01:00
David Shah
f5bfd557b6 python: Infrastructure for generic arch Python API 
Signed-off-by: David Shah <dave@ds0.me>
 2019-04-02 15:30:01 +01:00
David Shah
02ae21d8fc Add --placer option and refactor placer selection 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-24 11:10:20 +00:00
Eddie Hung
2d39cde17b Merge remote-tracking branch 'origin/master' into timingapi 2018-11-13 12:12:11 -08:00
Eddie Hung
3b2b15dc4a
Merge pull request #107 from YosysHQ/router_improve 
Major rewrite of "router1"
 2018-11-13 11:39:51 -08:00
Pedro Vanzella
710ea1b265 Mark getArchOptions as override in derived classes 2018-11-13 11:03:48 -02:00
David Shah
dab70466cd generic: Update arch to new timing API 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
Clifford Wolf
f93129634b Add getConflictingWireWire() arch API, streamline getConflictingXY semantic 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 17:28:41 +01:00
Clifford Wolf
d2bdb670c0 Add getConflictingPipWire() arch API, router1 improvements 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 11:34:38 +01:00
David Shah
ea03aafc26 clangformat 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-30 15:13:18 +01:00
Clifford Wolf
26be6f9761
Merge pull request #47 from YosysHQ/settings_propagate 
Use settings for placer1 and router1
 2018-08-18 19:25:19 +02:00
Clifford Wolf
428f0b9eba Add Arch attrs API 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-14 17:16:14 +02:00
Miodrag Milanovic
93a0d24560 Use settings for placer1 and router1 2018-08-09 18:39:10 +02:00
David Shah
ed602baa06
Merge pull request #42 from YosysHQ/floorplan 
Add basic data structures for floorplanning
 2018-08-09 10:49:11 +02:00
Clifford Wolf
5ddde5c49f Add pip locations 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-09 10:39:53 +02:00
Miodrag Milanovic
61bce47f3c Use settings for json and pcf 2018-08-08 20:14:18 +02:00
Clifford Wolf
f6189e4677 Merge branch 'master' of github.com:YosysHQ/nextpnr into constids 2018-08-08 19:35:13 +02:00
David Shah
cd4e761bb7
Merge pull request #44 from YosysHQ/improve_timing_spec 
Speed up budget allocator using topographical ordering and update cell timing API
 2018-08-08 19:23:47 +02:00
Miodrag Milanovic
fc5cee6fb8 clangformat 2018-08-08 18:17:34 +02:00
Clifford Wolf
abf5ea84b9 Get rid of BelType and PortPin in generic arch 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-08 17:22:05 +02:00
David Shah
433ad6462e Arch API: Removing Arch::isIOCell 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 17:06:59 +02:00
David Shah
bf42e525cb Arch API: New specification for timing port classes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 14:37:59 +02:00