Commit Graph

192 Commits

Author SHA1 Message Date
rowanG077
914999673c Rip out budgets 2023-06-20 10:57:10 +02:00
gatecat
603b60da8d api: add explain_invalid option to isBelLocationValid
Signed-off-by: gatecat <gatecat@ds0.me>
2022-12-07 10:27:58 +01:00
gatecat
e260ac33ab refactor: ArcBounds -> BoundingBox
Signed-off-by: gatecat <gatecat@ds0.me>
2022-12-07 10:00:53 +01:00
gatecat
c62a947a28 api: Make NetInfo* of checkPipAvailForNet const
Signed-off-by: gatecat <gatecat@ds0.me>
2022-12-02 14:20:39 +01:00
gatecat
a920ffcf70 ice40: implement checkPipAvailForNet
Signed-off-by: gatecat <gatecat@ds0.me>
2022-09-20 14:15:10 +02:00
gatecat
ddb084e9a8 archapi: Use arbitrary rather than actual placement in predictDelay
This makes predictDelay be based on an arbitrary belpin pair rather
than a arc of a net based on cell placement. This way 'what-if'
decisions can be evaluated without actually changing placement;
potentially useful for parallel placement.

A new helper predictArcDelay behaves like the old predictDelay to
minimise the impact on existing passes; only arches need be updated.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-12-19 17:15:15 +00:00
gatecat
2ffb081442 Fixing old emails and names in copyrights
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-12 13:22:38 +01:00
gatecat
ecc19c2c08 Using hashlib in arches
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 15:05:19 +01:00
Keith Rothman
fe4608386e Split nextpnr.h to allow for linear inclusion.
"nextpnr.h" is no longer the god header.  Important improvements:

 - Functions in log.h can be used without including
   BaseCtx/Arch/Context. This means that log_X functions can be called
   without included "nextpnr.h"

 - NPNR_ASSERT can be used without including "nextpnr.h" by including
   "nextpnr_assertions.h".  This allows NPNR_ASSERT to be used safely in
   any header file.

 - Types defined in "archdefs.h" are now available without including
   BaseCtx/Arch/Context.  This means that utility classes that will be
   used inside of BaseCtx/Arch/Context can be defined safely in a
   self-contained header.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-15 09:05:23 -07:00
gatecat
7922b3bfc4 Replace DelayInfo with DelayPair/DelayQuad
This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.

This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.

While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-19 11:31:33 +00:00
gatecat
c7c13cd95f Remove isValidBelForCell
This Arch API dates from when we were first working out how to
implement placement validity checking, and in practice is little used by
the core parts of placer1/HeAP and the Arch implementation involves a
lot of duplication with isBelLocationValid.

In the short term; placement validity checking is better served by the
combination of checkBelAvail and isValidBelForCellType before placement;
followed by isBelLocationValid after placement (potentially after
moving/swapping multiple cells).

Longer term, removing this API makes things a bit cleaner for a new
validity checking API.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-16 13:31:36 +00:00
Keith Rothman
99e397000c Add getBelHidden and add some missing "override" statements.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-11 14:58:02 -08:00
gatecat
11db5a2f1d Add BaseArchRanges for default ArchRanges types
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-09 10:39:14 +00:00
D. Shah
efca63862c Use 'T' postfix to disambiguate LHS and RHS of using
Arches might otherwise have range types named ambigiously with the entry
in ArchRanges.

Signed-off-by: D. Shah <dave@ds0.me>
2021-02-08 10:29:50 +00:00
D. Shah
3e631fe2f4 Add archArgs and archArgsToId to Arch API
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-05 19:19:17 +00:00
D. Shah
59c3db46ca ice40: Switch to BaseArch
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-05 19:19:17 +00:00
Keith Rothman
c99fbde0eb Mark IdString and IdStringList single argument constructors explicit.
Single argument constructors will silently convert to that type.  This
is typically not the right thing to do.  For example, the nexus and
ice40 arch_pybindings.h files were incorrectly parsing bel name strings,
etc.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:07 -08:00
D. Shah
a09a62bc4a ice40: Use snake case for arch-specific functions
This makes the difference clearer between the general arch API that
everyone must implement; and helper functions specific to one arch.

Signed-off-by: D. Shah <dave@ds0.me>
2021-02-03 10:46:12 +00:00
D. Shah
b31b21fd51 ice40: Implement IdStringList for all arch object names
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-02 17:00:33 +00:00
D. Shah
ff92d19fed arch: Add getNameDelimiter API for string lists
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-02 16:59:40 +00:00
Keith Rothman
da74a425d2 Run "make clangformat".
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-02 07:44:49 -08:00
Keith Rothman
9fe546f279 Rename Partition -> BelBucket.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-02 07:34:56 -08:00
Keith Rothman
0338368afa Add Partition APIs to ice40, nexus, gowin archs.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-02 07:34:56 -08:00
Keith Rothman
2285c8dbbd Initial refactoring of placer API.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-02 07:34:56 -08:00
D. Shah
94e8847d67 cleanup: Spelling fixes
Signed-off-by: D. Shah <dave@ds0.me>
2021-01-28 15:19:06 +00:00
D. Shah
75ee2fc4e6 Move RelPtr/RelSlice out of arches into common
The bba approach seems widely used enough that it's reasonable for this
to become part of common code.

Signed-off-by: D. Shah <dave@ds0.me>
2021-01-27 20:43:01 +00:00
D. Shah
c10238de8c ice40: Switch from RelPtr to RelSlice
This replaces RelPtrs and a separate length field with a Rust-style
slice containing both a pointer and a length; with bounds checking
always enforced.

Thus iterating over these structures is both cleaner and safer.

Signed-off-by: D. Shah <dave@ds0.me>
2021-01-27 18:35:49 +00:00
David Shah
8686b6dada RelPtr: remove copy constructor and copy assignment
These operations are meaningless for a data structure that references
another structure relative to its location.

Signed-off-by: David Shah <dave@ds0.me>
2020-11-13 20:19:53 +00:00
David Shah
b18ea204c2 Remove wire alias API
It has not actually been implemented in any router for over 2.5 years and causes nothing more than confusion. It can always be added back if it forms part of a future solution; possibly as part of a more general database structure rethink.

Signed-off-by: David Shah <dave@ds0.me>
2020-10-15 09:36:15 +01:00
Miodrag Milanovic
32ddc94b4f Support rest of parts 2020-07-08 14:09:44 +02:00
Miodrag Milanovic
6991a53d68 Adding LP4K as well 2020-07-08 13:44:13 +02:00
Miodrag Milanovic
3be76a837d Support 4K parts directly 2020-07-08 13:22:59 +02:00
whitequark
89e0cc8078 Simplify and improve chipdb embedding/loading. 2020-06-26 08:36:07 +00:00
whitequark
1dc1164dce CMake: rewrite chipdb handling from ground up. 2020-06-25 14:03:37 +00:00
David Shah
ce144addb3 ice40: Implement getRouteBoundingBox for router2
Signed-off-by: David Shah <dave@ds0.me>
2020-02-03 12:00:05 +00:00
David Shah
7123209324 Allow selection of router algorithm
Signed-off-by: David Shah <dave@ds0.me>
2020-02-03 11:54:38 +00:00
David Shah
02ae21d8fc Add --placer option and refactor placer selection
Signed-off-by: David Shah <dave@ds0.me>
2019-03-24 11:10:20 +00:00
Simon Schubert
7044f56246 ice40: support u4k 2019-02-23 17:39:20 +01:00
Miodrag Milanovic
73f200fe74 Load chipdb from filesystem as option 2019-02-09 13:34:57 +01:00
David Shah
cc53c312de timing: Path related fixes
Signed-off-by: David Shah <dave@ds0.me>
2019-01-27 16:45:37 +00:00
Sylvain Munaut
a79f0db749 ice40: Add helper to know which global network is driven by a SB_GB Bel
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-26 12:51:14 +01:00
Sylvain Munaut
3f4dc7c80e ice40: Add GlobalNetowkrInfo in the chip database
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
Sylvain Munaut
b29165eeba ice40/arch: Add helper to check if a BEL is LOCKED or not
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-19 18:20:20 +01:00
Eddie Hung
c5ba77e06b Merge remote-tracking branch 'origin/master' into timingapi 2018-11-13 13:47:37 -08:00
Eddie Hung
51a2894762 [ice40] getBudgetOverride() to use constrained Z not placed Z 2018-11-13 12:51:46 -08:00
Eddie Hung
2d39cde17b Merge remote-tracking branch 'origin/master' into timingapi 2018-11-13 12:12:11 -08:00
Eddie Hung
3b2b15dc4a
Merge pull request #107 from YosysHQ/router_improve
Major rewrite of "router1"
2018-11-13 11:39:51 -08:00
David Shah
07e265868b archapi: Add getDelayFromNS to improve timing algorithm portability
Signed-off-by: David Shah <dave@ds0.me>
2018-11-12 14:03:58 +00:00
David Shah
122771cac3 timing: iCE40 Arch API changes for clocking info
Signed-off-by: David Shah <dave@ds0.me>
2018-11-12 14:03:58 +00:00
Clifford Wolf
6002a0a80a clangformat
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-11 19:48:15 +01:00