Commit Graph

927 Commits

Author SHA1 Message Date
Stefan Riesenberger
e9ce55bfd0 ice40: fix crash when packing LUTs with no output 2022-03-14 12:43:19 +01:00
gatecat
86699b42f6 Switch to potentially-sparse net users array
This uses a new data structure for net.users that allows gaps, so
removing a port from a net is no longer an O(n) operation on the number
of users the net has.

Signed-off-by: gatecat <gatecat@ds0.me>
2022-02-27 13:47:05 +00:00
gatecat
6a32aca4ac refactor: New member functions to replace design_utils
Signed-off-by: gatecat <gatecat@ds0.me>
2022-02-18 11:13:18 +00:00
gatecat
76683a1e3c refactor: Use constids instead of id("..")
Signed-off-by: gatecat <gatecat@ds0.me>
2022-02-16 17:09:54 +00:00
gatecat
9ef0bc3d3a refactor: Use cell member functions to add ports
Signed-off-by: gatecat <gatecat@ds0.me>
2022-02-16 16:45:45 +00:00
gatecat
30fd86ce69 refactor: New NetInfo and CellInfo constructors 2022-02-16 15:10:57 +00:00
gatecat
58a1b473b8
Merge pull request #873 from YosysHQ/gatecat/ice40-carry-lut
ice40: Pack LUT at start of carry chain if there is 1 candidate
2022-01-16 19:59:56 +00:00
gatecat
ddb084e9a8 archapi: Use arbitrary rather than actual placement in predictDelay
This makes predictDelay be based on an arbitrary belpin pair rather
than a arc of a net based on cell placement. This way 'what-if'
decisions can be evaluated without actually changing placement;
potentially useful for parallel placement.

A new helper predictArcDelay behaves like the old predictDelay to
minimise the impact on existing passes; only arches need be updated.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-12-19 17:15:15 +00:00
gatecat
a946ed0206 ice40: Pack LUT at start of carry chain if there is 1 candidate
Signed-off-by: gatecat <gatecat@ds0.me>
2021-12-14 19:27:20 +00:00
gatecat
8f722a0d35 ice40: Use default value when IP is missing BUS_ADDR74 parameter
Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-20 16:08:26 +01:00
gatecat
d290766101 ice40: Fix order of values in error
Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-10 23:23:19 +01:00
gatecat
2ffb081442 Fixing old emails and names in copyrights
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-12 13:22:38 +01:00
gatecat
dcbb322447 Remove redundant code after hashlib move
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 15:05:20 +01:00
gatecat
eca1a4cee4 Use hashlib in most remaining code
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 15:05:20 +01:00
gatecat
ecc19c2c08 Using hashlib in arches
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 15:05:19 +01:00
gatecat
f4fed62c05 Use hashlib in routers
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 15:04:53 +01:00
gatecat
579b98c596 Use hashlib for core netlist structures
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 14:27:56 +01:00
gatecat
ff72454f83 Add hash() member functions
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 14:27:56 +01:00
gatecat
6a3eacddd6 Add default base implementation of cluster API
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-06 11:47:06 +01:00
Keith Rothman
fe4608386e Split nextpnr.h to allow for linear inclusion.
"nextpnr.h" is no longer the god header.  Important improvements:

 - Functions in log.h can be used without including
   BaseCtx/Arch/Context. This means that log_X functions can be called
   without included "nextpnr.h"

 - NPNR_ASSERT can be used without including "nextpnr.h" by including
   "nextpnr_assertions.h".  This allows NPNR_ASSERT to be used safely in
   any header file.

 - Types defined in "archdefs.h" are now available without including
   BaseCtx/Arch/Context.  This means that utility classes that will be
   used inside of BaseCtx/Arch/Context can be defined safely in a
   self-contained header.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-15 09:05:23 -07:00
gatecat
7922b3bfc4 Replace DelayInfo with DelayPair/DelayQuad
This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.

This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.

While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-19 11:31:33 +00:00
gatecat
c7c13cd95f Remove isValidBelForCell
This Arch API dates from when we were first working out how to
implement placement validity checking, and in practice is little used by
the core parts of placer1/HeAP and the Arch implementation involves a
lot of duplication with isBelLocationValid.

In the short term; placement validity checking is better served by the
combination of checkBelAvail and isValidBelForCellType before placement;
followed by isBelLocationValid after placement (potentially after
moving/swapping multiple cells).

Longer term, removing this API makes things a bit cleaner for a new
validity checking API.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-16 13:31:36 +00:00
Keith Rothman
99e397000c Add getBelHidden and add some missing "override" statements.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-11 14:58:02 -08:00
gatecat
11db5a2f1d Add BaseArchRanges for default ArchRanges types
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-09 10:39:14 +00:00
gatecat
bcf81f0e71
Merge pull request #568 from YosysHQ/dave/arch-override
Create a new BaseArch that formally specifies the Arch API and provides some base implementations
2021-02-08 17:56:08 +00:00
D. Shah
0d444bfc6e Use RelSlice::ssize instead of cast-to-int throughout
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-08 11:24:00 +00:00
D. Shah
efca63862c Use 'T' postfix to disambiguate LHS and RHS of using
Arches might otherwise have range types named ambigiously with the entry
in ArchRanges.

Signed-off-by: D. Shah <dave@ds0.me>
2021-02-08 10:29:50 +00:00
D. Shah
3e631fe2f4 Add archArgs and archArgsToId to Arch API
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-05 19:19:17 +00:00
D. Shah
59c3db46ca ice40: Switch to BaseArch
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-05 19:19:17 +00:00
Keith Rothman
c99fbde0eb Mark IdString and IdStringList single argument constructors explicit.
Single argument constructors will silently convert to that type.  This
is typically not the right thing to do.  For example, the nexus and
ice40 arch_pybindings.h files were incorrectly parsing bel name strings,
etc.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:07 -08:00
D. Shah
a09a62bc4a ice40: Use snake case for arch-specific functions
This makes the difference clearer between the general arch API that
everyone must implement; and helper functions specific to one arch.

Signed-off-by: D. Shah <dave@ds0.me>
2021-02-03 10:46:12 +00:00
D. Shah
b31b21fd51 ice40: Implement IdStringList for all arch object names
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-02 17:00:33 +00:00
D. Shah
9388df19d3 refactor: Replace getXName().c_str(ctx) with ctx->nameOfX
This makes the ongoing migration to IdStringList easier.

Signed-off-by: D. Shah <dave@ds0.me>
2021-02-02 17:00:14 +00:00
D. Shah
ff92d19fed arch: Add getNameDelimiter API for string lists
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-02 16:59:40 +00:00
Keith Rothman
da74a425d2 Run "make clangformat".
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-02 07:44:49 -08:00
Keith Rothman
9089ee2d16 Add pybindings for new APIs.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-02 07:43:36 -08:00
Keith Rothman
9fe546f279 Rename Partition -> BelBucket.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-02 07:34:56 -08:00
Keith Rothman
0338368afa Add Partition APIs to ice40, nexus, gowin archs.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-02 07:34:56 -08:00
Keith Rothman
2285c8dbbd Initial refactoring of placer API.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-02 07:34:56 -08:00
Keith Rothman
5cf2f8d1ea Seperate PipRange types in pybindings_shared.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-01 10:23:21 -08:00
D. Shah
94e8847d67 cleanup: Spelling fixes
Signed-off-by: D. Shah <dave@ds0.me>
2021-01-28 15:19:06 +00:00
D. Shah
6ecf7f86c8 cleanup: Remove dead/unused code
Note that some '#if 0' code that might still be useful for debugging in
the future has been retained.

Signed-off-by: D. Shah <dave@ds0.me>
2021-01-28 14:59:13 +00:00
D. Shah
75ee2fc4e6 Move RelPtr/RelSlice out of arches into common
The bba approach seems widely used enough that it's reasonable for this
to become part of common code.

Signed-off-by: D. Shah <dave@ds0.me>
2021-01-27 20:43:01 +00:00
D. Shah
c10238de8c ice40: Switch from RelPtr to RelSlice
This replaces RelPtrs and a separate length field with a Rust-style
slice containing both a pointer and a length; with bounds checking
always enforced.

Thus iterating over these structures is both cleaner and safer.

Signed-off-by: D. Shah <dave@ds0.me>
2021-01-27 18:35:49 +00:00
David Shah
74c4fa6751 ice40: Nicer error for unconstrained SB_GB_IO
Signed-off-by: David Shah <dave@ds0.me>
2020-12-27 20:11:08 +00:00
Tim Callahan
c967f8e434 Use std::string::find(char c) when searching for a single character.
Signed-off-by: Tim Callahan <tcal@google.com>
2020-12-16 20:07:56 -08:00
David Shah
92ef01830c ice40: Clarify feedback paths in PLL constraints code
Signed-off-by: David Shah <dave@ds0.me>
2020-12-03 11:40:00 +00:00
David Shah
940b7efa15 ice40: Derive PLL timing constraints
Signed-off-by: David Shah <dave@ds0.me>
2020-12-03 09:55:30 +00:00
David Shah
8686b6dada RelPtr: remove copy constructor and copy assignment
These operations are meaningless for a data structure that references
another structure relative to its location.

Signed-off-by: David Shah <dave@ds0.me>
2020-11-13 20:19:53 +00:00
Sylvain Munaut
bdc95b8dc0 ice40/pack/SB_PLL: Force fixed value to 4'b1111 if dynamic delay is used
It's been confirmed that :
 (1) this is required by the hardware
 (2) icecube will force that field to 4'b1111 in fixed mode

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2020-11-10 10:24:58 +01:00
David Shah
b18ea204c2 Remove wire alias API
It has not actually been implemented in any router for over 2.5 years and causes nothing more than confusion. It can always be added back if it forms part of a future solution; possibly as part of a more general database structure rethink.

Signed-off-by: David Shah <dave@ds0.me>
2020-10-15 09:36:15 +01:00
whitequark
f6d436d58b
CMake: fix Windows-ism in status message 2020-08-26 09:51:38 +00:00
William D. Jones
e63270f918 Fix MESSAGE indicating where externally-built .bbas live. 2020-08-22 21:09:21 -04:00
Miodrag Milanovic
8f2b707d02 Initial conversion to pybind11 2020-07-23 18:35:18 +02:00
Sylvain Munaut
33067130e5 ice40: If IO is used by SB_GB_IO, can't use it for PLL
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2020-07-09 13:04:19 +02:00
Miodrag Milanovic
2726f3af91 Fixes for new part types 2020-07-08 16:45:27 +02:00
Miodrag Milanovic
1fae965cbb Use proper names in GUI 2020-07-08 14:16:00 +02:00
Miodrag Milanovic
32ddc94b4f Support rest of parts 2020-07-08 14:09:44 +02:00
Miodrag Milanovic
b45b375ff2 Missed adding option 2020-07-08 13:45:34 +02:00
Miodrag Milanovic
6991a53d68 Adding LP4K as well 2020-07-08 13:44:13 +02:00
Miodrag Milanovic
3be76a837d Support 4K parts directly 2020-07-08 13:22:59 +02:00
David Shah
137241cfef
Merge pull request #463 from YosysHQ/fix-archcheck
Fix arch checks, and add these to CI
2020-07-02 13:32:30 +01:00
whitequark
f6e30f22f4 CMake: fix path checks in chipdb build scripts.
`if(NOT DEFINED)` is not appropriate since a variable that contains
`-NOTFOUND` still counts as `DEFINED`. This can cause issues if
configuration fails, writes `-NOTFOUND` to the cache, and is then
restarted.
2020-07-01 20:22:21 +00:00
David Shah
b24e0a609b ice40: Fix getBelsByTile
Signed-off-by: David Shah <dave@ds0.me>
2020-06-29 19:52:31 +01:00
Miodrag Milanovic
929a1cc7e4 Make python bindings consistent 2020-06-27 13:24:30 +02:00
Miodrag Milanovic
7a95629aff Fix clangformat and execute it 2020-06-27 13:20:16 +02:00
Miodrag Milanovic
901ad4e917 Update git ignore locations 2020-06-27 13:18:06 +02:00
whitequark
89e0cc8078 Simplify and improve chipdb embedding/loading. 2020-06-26 08:36:07 +00:00
whitequark
bf8d4c428e CMake: require at least version 3.5 (Ubuntu 16.04). 2020-06-25 14:03:37 +00:00
whitequark
1dc1164dce CMake: rewrite chipdb handling from ground up. 2020-06-25 14:03:37 +00:00
Sylvain Munaut
9b71bba747 ice40: Add fallback behavior for Extra Cell config bits vectors
This helps make new nextpnr compatible with old chipdbs when a parameters
goes from single bit to multi bit.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2020-06-02 20:21:16 +02:00
Sylvain Munaut
5e2b6bcef9 ice40: Add support for the 2nd bit of SHIFTREG_DIV_MODE
This requires the matching chipdb update from icestorm project !

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2020-06-02 11:03:04 +02:00
David Shah
f44498a530
Merge pull request #447 from whitequark/wasi
Port nextpnr-{ice40,ecp5} to WASI
2020-05-24 14:23:35 +01:00
whitequark
e7bb04769d Port nextpnr-{ice40,ecp5} to WASI.
This involves very few changes, all typical to WASM ports:
  * WASM doesn't currently support threads or atomics so those are
    disabled.
  * WASM doesn't currently support exceptions so the exception
    machinery is stubbed out.
  * WASM doesn't (and can't) have mmap(), so an emulation library is
    used. That library currently doesn't support MAP_SHARED flags,
    so MAP_PRIVATE is used instead.

There is also an update to bring ECP5 bbasm CMake rules to parity
with iCE40 ones, since although it is possible to embed chipdb into
nextpnr on WASM, a 200 MB WASM file has very few practical uses.

The README is not updated and there is no included toolchain file
because at the moment it's not possible to build nextpnr with
upstream boost and wasi-libc. Boost requires a patch (merged, will
be available in boost 1.74.0), wasi-libc requires a few unmerged
patches.
2020-05-23 20:57:26 +00:00
Nathaniel Graff
08f68518f2 Fix spelling of 'unsupported'
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2020-05-13 20:00:37 -07:00
David Shah
98e2f9ea81 ice40: Derive oscillator frequency constraints
Signed-off-by: David Shah <dave@ds0.me>
2020-03-29 21:02:16 +01:00
Sylvain Munaut
bd68d6035c ice40: Fix output register timing analysis for registered output enable
Wrong bits were being tested. [5:4] is what's controlling the output
enable path.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2020-03-29 10:27:42 +02:00
David Shah
a621e04062 ice40: Always copy DFF attrs to LC
Signed-off-by: David Shah <dave@ds0.me>
2020-03-19 21:35:31 +00:00
David Shah
bb73580209
Merge pull request #400 from YosysHQ/dave/tri-fixes
Improve handling of unused inout port bits
2020-03-10 13:50:59 +00:00
Sylvain Munaut
054be6fb67 build: Default the ECP5 and iCE40 roots to the install prefix
If the user specifies a custom install prefix, chances are icestrom/trellis
are also in that prefix rather than the hardcoded /usr/local

Fixes #351

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2020-03-03 15:32:10 +01:00
David Shah
9aa22433ff Improve handling of unused inout port bits
Signed-off-by: David Shah <dave@ds0.me>
2020-02-25 14:26:47 +00:00
David Shah
2248e07b66 router2: Improve flow and log output
Signed-off-by: David Shah <dave@ds0.me>
2020-02-03 13:46:05 +00:00
David Shah
ce144addb3 ice40: Implement getRouteBoundingBox for router2
Signed-off-by: David Shah <dave@ds0.me>
2020-02-03 12:00:05 +00:00
David Shah
7123209324 Allow selection of router algorithm
Signed-off-by: David Shah <dave@ds0.me>
2020-02-03 11:54:38 +00:00
Larry Doolittle
eba6ea53f8 More adjustments to .bba file locations
Follows PM discussion with Marcus Comstedt.
Extend changes in .bba file location (made in commit b6a7b60) to ice40 and MSVC cases,
  so all cases become compatible with read-only access to git tree.
Only known down-side is inefficiency when building out-of-tree for multiple architectures;
  people following that use case should consider using PREGENERATED_BBA_PATH.
It would be nice if there were less copy-paste in MSVC vs. non-MSVC content in family.cmake,
  but that would have to be addressed by someone more skilled in Cmake and MSVC.
2020-01-14 12:28:40 -08:00
David Shah
fe40094216 Preserve hierarchy through packing
Signed-off-by: David Shah <dave@ds0.me>
2019-12-27 10:44:30 +00:00
David Shah
b100087024 python: Add bindings for hierarchy structures
Signed-off-by: David Shah <dave@ds0.me>
2019-12-27 10:44:30 +00:00
David Shah
035bfb0fe5 json: Remove legacy frontend
Signed-off-by: David Shah <dave@ds0.me>
2019-12-27 10:44:30 +00:00
David Shah
28279b18fe frontend/generic: Fix regressions
Signed-off-by: David Shah <dave@ds0.me>
2019-12-27 10:44:30 +00:00
David Shah
b6e2159cec Work around Qt MOC issue with IdString enums
Signed-off-by: David Shah <dave@ds0.me>
2019-12-27 10:32:23 +00:00
David Shah
dd7f7a53bd ice40: Improve error handling of Lattice-style parameters
Signed-off-by: David Shah <dave@ds0.me>
2019-12-10 15:28:16 +00:00
Clifford Wolf
0392cd3a5b Add bba #embed support
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-12-01 00:44:07 +01:00
David Shah
ff9d6b4f89 ice40: Make HeAP the default placer
Signed-off-by: David Shah <dave@ds0.me>
2019-11-26 10:03:28 +00:00
David Shah
d08e2ade88
Merge pull request #345 from YosysHQ/dave/sdf
Improve handling of top level IO and add SDF support
2019-11-18 14:28:40 +00:00
David Shah
f2b9cc6d23 sdf: Working on support for CVC
Signed-off-by: David Shah <dave@ds0.me>
2019-10-24 12:37:07 +01:00
Sean Cross
5b99382002 ice40: cmake: fix build with pregenerated bba path
When building using non-pregenerated bba files, the rule to create bbasm
files gets called twice: once unconditionally, and once as part of the
conditional that determines we're not using a pregenerated bba path.

If we _are_ using a pregenerated bba path, then this rule gets called
anyway, resulting in a build error.

Remove the duplicate, unconditional creation of the bba file generation,
to fix the build when using pregenerated files, and to speed up the
build when not using pregenerated files.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-10-24 13:39:00 +08:00
David Shah
a22f86f861 ice40: Preserve top level IO properly
Signed-off-by: David Shah <dave@ds0.me>
2019-10-19 13:01:00 +01:00
David Shah
8c0610e84f ice40: Add set_frequency pcf command; and document pcf
Signed-off-by: David Shah <dave@ds0.me>
2019-10-13 18:48:39 +01:00
David Shah
30e3c8469b ice40: Add support for PLL DELAY_ADJUSTMENT_MODE
Fixes #336

Signed-off-by: David Shah <dave@ds0.me>
2019-09-23 19:46:31 +01:00
David Shah
fac998ddcb ice40: Fix carry feed-out when we have to split the chain next
Signed-off-by: David Shah <dave@ds0.me>
2019-09-23 15:51:05 +01:00