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927 Commits

Author SHA1 Message Date
David Shah
d27ec2cd15 ice40: Don't constrain to a PLL bel that has already been used 
Fixes #258

Signed-off-by: David Shah <dave@ds0.me>
 2019-04-01 12:25:32 +01:00
Sylvain Munaut
d401e3e1a0 ice40: Add support for SB_I2C and SB_SPI 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-03-25 23:48:59 +01:00
David Shah
02ae21d8fc Add --placer option and refactor placer selection 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-24 11:10:20 +00:00
David Shah
bd12c0a486 HeAP: Add PlacerHeapCfg 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:31:54 +00:00
David Shah
7142db28a8 HeAP: Make HeAP placer optional 
A CMake option 'BUILD_HEAP' (default on) configures building of the
HeAP placer and the associated Eigen3 dependency.

Default for the iCE40 is SA placer, with --heap-placer to use HeAP

Default for the ECP5 is HeAP placer, as SA placer can take 1hr+ for
large ECP5 designs and HeAP tends to give better QoR. --sa-placer can
be used to use SA instead, and auto-fallback to SA if HeAP not built.

Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:31:54 +00:00
David Shah
ea56dc9d08 HeAP: Add TAUCS wrapper and integration 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:31:54 +00:00
David Shah
1780f42b9a ice40: Add examples folder including floorplan example 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:31:54 +00:00
David Shah
493d6c3fb9 Add Python helper functions for floorplanning 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:31:54 +00:00
Marcin Kościelnicki
1060810d7a ice40: Fix u4k in external chipdb mode. 
Signed-off-by: Marcin Kościelnicki <marcin@symbioticeda.com>
 2019-03-19 15:23:43 +01:00
David Shah
e87fb69665 ice40: u4k merge fix 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-25 11:36:12 +00:00
David Shah
7a5699891a
Merge pull request #239 from YosysHQ/dsp_casc_dummy_wires 
ice40: Add DSP SIGNEXTIN/OUT and ACCUMCI/O ports
 2019-02-25 08:20:32 +00:00
Simon Schubert
7044f56246 ice40: support u4k 2019-02-23 17:39:20 +01:00
David Shah
a05f6b261e ice40: Add DSP SIGNEXTIN/OUT and ACCUMCI/O ports 
Signed-off-by: David Shah <davey1576@gmail.com>
 2019-02-21 20:34:23 +00:00
David Shah
a7ea3f58e3 ice40: Fix timing class of 'padin' GB outputs 
Signed-off-by: David Shah <davey1576@gmail.com>
 2019-02-20 21:23:43 +00:00
Miodrag Milanović
c52202233a
Merge branch 'master' into mmaped_chipdb 2019-02-12 18:53:20 +01:00
Miodrag Milanovic
8b0af0e48d Fix according to comments on PR 2019-02-10 08:33:52 +01:00
David Shah
054be887ae ice40: PLLs can't conflict with themselves 
Fixes error building testcase from #145

Signed-off-by: David Shah <dave@ds0.me>
 2019-02-09 19:27:52 +00:00
Miodrag Milanovic
73f200fe74 Load chipdb from filesystem as option 2019-02-09 13:34:57 +01:00
David Shah
170bf8a5ec ice40: Don't create PLLOUT_B buffer for single-output PLL variants 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-09 10:41:22 +00:00
Eddie Hung
6d664046d3
Merge pull request #220 from YosysHQ/coi3 
ice40: Add budget override for CO->I3 path
 2019-01-29 11:22:31 -08:00
Eddie Hung
77bb5ea63a [ice40] Refactor Arch::getBudgetOverride() 2019-01-29 10:43:14 -08:00
David Shah
cc53c312de timing: Path related fixes 
Signed-off-by: David Shah <dave@ds0.me>
 2019-01-27 16:45:37 +00:00
David Shah
f4d8a25fb7 ice40: Add budget override for CO->I3 path 
Signed-off-by: David Shah <dave@ds0.me>
 2019-01-27 14:43:10 +00:00
David Shah
265fa1be16
Merge pull request #211 from smunaut/ice40_ram_attrs 
ice40/pack: Copy attributes to packed cell
 2019-01-21 11:10:38 +00:00
Sylvain Munaut
b274a8f8f0 ice40/pack: Copy attributes to packed RAM cells 
Useful to allow manual placement of SPRAM/EBR using BEL attribute
for instance

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-01-19 15:49:21 +01:00
Sylvain Munaut
830d462f92 ice40: Add error message if a selected site is not Global Buffer capable 
... rather than assert()-out during the call to getWireBelPins() call

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-01-18 17:53:24 +01:00
David Shah
7d8b729ff4 ice40: Add timing data for all IO modes 
Signed-off-by: David Shah <dave@ds0.me>
 2019-01-07 17:18:40 +00:00
David Shah
4444a39fd4 ice40: Improve handling of unconstrained IO 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-26 16:00:19 +00:00
David Shah
953a3ac552 ice40: Add PCF support for -pullup, -pullup_resistor and -nowarn 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-12-20 20:52:54 +00:00
David Shah
75335d4e1a ice40: Fix LOCK feedthrough insertion with carry or >8 LUTs 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-12-20 18:50:34 +00:00
David Shah
51155ec6a7 ci: Add attosoc smoketest for ice40 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-12-08 17:09:27 +00:00
David Shah
d790d0bb91
Merge pull request #163 from daveshah1/timing_opt 
Adding criticality calculation and experimental timing optimisation pass
 2018-12-07 21:19:41 +00:00
David Shah
144363693d ice40: Report error for unsupported PLL FEEDBACK_PATH values 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-06 11:29:33 +00:00
David Shah
e7fc42ac84 ice40: Improve bitstream error handling 
Fixes #161 and provides a clearer error for #170

Signed-off-by: David Shah <dave@ds0.me>
 2018-12-06 11:19:48 +00:00
David Shah
b732e42fa3 timing_opt: Reduce iterations to 30, tidy up logging 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-06 11:00:16 +00:00
David Shah
f53dc8d3c9 timing_opt: Improve heuristics 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-06 10:53:01 +00:00
David Shah
f3adf5a576 timing_opt: Make an optional pass controlled by command line 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-06 10:53:01 +00:00
David Shah
254c5ea359 clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-06 10:53:01 +00:00
David Shah
b51308708b timing_opt: Debugging and integration 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-06 10:53:01 +00:00
David Shah
88e1e6bdf4 clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-06 10:52:46 +00:00
David Shah
dbaabae235 ice40: Put debug logging behind ctx->debug 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-06 10:51:17 +00:00
David Shah
d298687dc2 ice40: Fix carry chain splitting 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-05 10:12:23 +00:00
David Shah
51cda136b1 ice40: Don't split carry chain in simple feed-out cases 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-04 12:31:32 +00:00
David Shah
0c93b55650 ice40: Include I3 connectivity in chain 
Thanks @smunaut

Signed-off-by: David Shah <dave@ds0.me>
 2018-12-04 12:02:26 +00:00
whitequark
7fad6058bd ice40: add reset global promotion threshold. 2018-12-04 07:40:55 +00:00
Daniel Serpell
d4b3c1d819 ice40: Add support for placing SB_LEDDA_IP block. 
Signed-off-by: Daniel Serpell <daniel.serpell@gmail.com>
 2018-12-01 22:27:04 -03:00
David Shah
8af367ad0a ice40: Add a warning for unconstrained IO 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-29 19:35:19 +00:00
David Shah
4e05d09397 Improve reporting of unknown cell types 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-29 19:26:23 +00:00
David Shah
fc08856537
Merge pull request #157 from whitequark/fanout-thresh 
ice40: raise CE global promotion threshold
 2018-11-29 09:12:47 +00:00
whitequark
db96b88d79 ice40: raise CE global promotion threshold. 2018-11-29 00:12:48 +00:00
whitequark
a974124a7a ice40: print fanout of nets promoted to globals. 2018-11-28 23:52:48 +00:00
David Shah
0872b63b0b
Merge pull request #155 from smunaut/issue_151 
ice40: Update the way LVDS inputs are handled during bitstream generation
 2018-11-28 16:20:36 +00:00
Sylvain Munaut
ba958d1792 ice40: Try to be helpful and suggest using PAD PLL instead of CORE 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-28 16:04:58 +01:00
Sylvain Munaut
a65b12e8d6 ice40: Revamp the whole PLL placement/validity check logic 
We do a pre-pass on all the PLLs to place them before packing.

To place them:
 - First pass with all the PADs PLLs since those can only fit at one
   specific BEL depending on the input connection
 - Second pass with all the dual outputs CORE PLLs. Those can go
   anywhere where there is no conflicts with their A & B outputs and
   used IO pins
 - Third pass with the single output CORE PLLs. Those have the least
   constrains.

 During theses passes, we also check the validity of all their connections.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-28 16:04:43 +01:00
Sylvain Munaut
5f0f2b060b ice40: Update the way LVDS inputs are handled during bitstream generation 
* Instead of "patching" input_en, we completely separate config for
   normal and LVDS pair.
   - For normal pair, nothing changes
   - For LVDS pairs, the IE/REN bits are always set as if the input buffer
     are disabled. Then if input_en was set to 1 (i.e. the input is
     actually for something), then we set the IoCtrl.LVDS bit.
   - Also for LVDS, if input is used, pullups are forcibly disabled.

 * When scanning for unused IOs, never process those part of a LVDS pair.
   They will have been configured by the complement

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-28 16:04:23 +01:00
David Shah
80f7ef4b4b ice40: Finer-grained control of global promotion 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-27 19:06:55 +00:00
Sylvain Munaut
584e8c58a6 ice40: During global promotion, only promote if this will actually fit ! 
We need to take into account the global networks that are already used
and possibly locked to know what we can promote since all networks
can't drive resets / clock-enables

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-26 12:51:14 +01:00
Sylvain Munaut
a79f0db749 ice40: Add helper to know which global network is driven by a SB_GB Bel 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-26 12:51:14 +01:00
David Shah
fe2fa0e3ed ice40: Improve PCF error handling 
Fixes #147

Signed-off-by: David Shah <dave@ds0.me>
 2018-11-26 09:34:28 +00:00
David Shah
2c6a2c40e1 Merge branch 'master' of github.com:YosysHQ/nextpnr 2018-11-26 09:23:31 +00:00
David Shah
2951e37b45 ice40: Fix disconnection of PACKAGEPIN for PAD PLLs 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-24 17:49:26 +00:00
David Shah
65a5d05952 python: Fixes to get net wires map working 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-22 13:42:20 +00:00
Sylvain Munaut
9c5f4fb885 ice40/pll: Fix typo when testing for global port output net 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-20 23:53:08 +01:00
Sylvain Munaut
e8556aff37 ice40: Add support for SB_RGBA_DRV 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
de8de6304f ice40: Add global network output support for LFOSC/HFOSC 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
271cc7be11 ice40/pack: Add helper to constain cells that are unique in the FPGA 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
519d4e2af8 ice40: Add support for SB_GB_IO 
During packing we replace them by standard SB_IO cells and create the
'fake' SB_GB that matches that IO site global buffer connection.

It's done in a separate pass because we need to make sure the nextpnr iob
have been dealt first so we have our final Bel location on the SB_IO.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
d8e4c21d96 ice40: Add support for PLL global outputs via PADIN 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
bc9f2da470 ice40: Introduce the concept of forPadIn SB_GB 
Those are cells that are created mainly to handle the various sources a
global network can be driven from other than a user net.

When the flag is set, this means the global network usually driven by
this BEL is in fact driven by something else and so that SB_GB BEL and
matching global network can't be used.

This is also what gets used to set the extra bits during bitstream
generation.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
325d46e284 ice40/chipdb: Add wires to global network for all cells that can drive it 
The icebox DB is a bit inconsistent in how global network connections
are represented. Here we make it appear consistent by creating ports
on the cells that can drive it.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
3f4dc7c80e ice40: Add GlobalNetowkrInfo in the chip database 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
c219d8fe4d ice40: Fix BEL validity check for PLL vs SB_IO 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
9483a95a4a ice40: Improve the is_sb_pll40_XXX predicates collection 
- Add a test for dual output PLL variant
 - Make them handle the packet version of the cell

 This will become useful for various tests during PLL rework

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
f6d6022984 ice40: Fix PLLTYPE for SB_PLL40_2F_PAD 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
ad23caef33 ice40/pll: Add proper support for PLLOUT_SELECT_xxx attributes 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
78f3c2c37d ice40: Make PLL default FEEDBACK_MODE to SIMPLE 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
35e9ec7737 ice40: Minor fix in predicate checking for logic port 
- is_sb_pll40 covers all the PLL types
 - Use helper to test for gbuf

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
ac5d767d4f ice40/pack: Stop looking for BEL when we have one during PLL placement 
Ideally we should first process all the PLL that are constrained somehow
(either explicitely or because they are PAD) and then free place the rest.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
5fb3353557 ice40/pack: Allow PLL to be constrained via 'BEL' attributes 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
8c69a3bba3 ice40/pack: Make sure we don't use a LOCKED bel when placing PLL 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
b29165eeba ice40/arch: Add helper to check if a BEL is LOCKED or not 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
70e1fe423f ice40/chipdb: Fix LOCKED keyword support to include all packages 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 13:12:43 +01:00
Sylvain Munaut
42fbb110fc ice40/bitstream: Handle IoCtrl.IE_ polarity when configuring unused SB_IO 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 13:12:43 +01:00
Sylvain Munaut
e1e8d8cd14 ice40: Add warning if an instanciated SB_IO has its PACKAGE_PIN used elsewhere 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-16 16:36:57 +01:00
Sylvain Munaut
01950a2349 ice40/bitstream: Convert to UNIX line endings 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-16 16:24:56 +01:00
David Shah
9c52afcf5f clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:25:51 +00:00
David Shah
20aa0a0eed ice40: Remove unnecessary RAM assertion 
Fixes #121

Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:18:53 +00:00
Eddie Hung
c5ba77e06b Merge remote-tracking branch 'origin/master' into timingapi 2018-11-13 13:47:37 -08:00
Eddie Hung
51a2894762 [ice40] getBudgetOverride() to use constrained Z not placed Z 2018-11-13 12:51:46 -08:00
Eddie Hung
2d39cde17b Merge remote-tracking branch 'origin/master' into timingapi 2018-11-13 12:12:11 -08:00
Eddie Hung
3b2b15dc4a
Merge pull request #107 from YosysHQ/router_improve 
Major rewrite of "router1"
 2018-11-13 11:39:51 -08:00
Pedro Vanzella
710ea1b265 Mark getArchOptions as override in derived classes 2018-11-13 11:03:48 -02:00
Clifford Wolf
06e0e1ffee Various router1 fixes, Add BelId/WireId/PipId::operator<() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-13 05:05:56 +01:00
David Shah
fc5e6bec9a timing: Add support for clock constraints 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
07e265868b archapi: Add getDelayFromNS to improve timing algorithm portability 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
e633aa09cc timing: Fix handling of clock inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
9687f7d1da Working on multi-clock analysis 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
122771cac3 timing: iCE40 Arch API changes for clocking info 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah
becf3021bd ice40: Don't set colbuf bits for 384 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-11-11 23:52:04 +01:00
Clifford Wolf
6002a0a80a clangformat 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 19:48:15 +01:00
Clifford Wolf
f93129634b Add getConflictingWireWire() arch API, streamline getConflictingXY semantic 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 17:28:41 +01:00
Clifford Wolf
d2bdb670c0 Add getConflictingPipWire() arch API, router1 improvements 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 11:34:38 +01:00
Miodrag Milanović
6b197fde72
Merge pull request #93 from YosysHQ/gui_changes 
Gui changes
 2018-11-10 23:00:34 -08:00
David Shah
8df72a1f34 ice40: Fix SPRAM and IO globals 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-04 14:13:53 +00:00
David Shah
af9ed378b4 ice40: Fix PLL DYNAMICDELAY 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-27 23:28:25 +02:00
Miodrag Milanovic
4c0db11608 fix grid dimensions for ice40 2018-10-27 12:02:01 +02:00
Miodrag Milanovic
69b9aaba9d ups, uncomment 2018-10-27 11:52:29 +02:00
Miodrag Milanovic
61b2fcf7da Fixed pip graphics 2018-10-27 11:50:40 +02:00
Eddie Hung
96efe48847
Merge pull request #88 from YosysHQ/issue72 
Resolve issue #72
 2018-10-11 02:54:19 -07:00
Clifford Wolf
b4dc6b8845 Add info message for promoted global nets 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-03 13:40:21 +02:00
David Shah
7ef8a7415d ice40: Add error for bad PACKAGE_PIN connections 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-03 12:14:49 +01:00
David Shah
a27c7b45de Refactor chain finder to its own file 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-30 16:29:26 +01:00
David Shah
ea03aafc26 clangformat 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-30 15:13:18 +01:00
Clifford Wolf
07cf349ee4
Merge pull request #79 from YosysHQ/ice40lvds 
ice40: Adding LVDS input support
 2018-09-25 18:21:56 +02:00
Clifford Wolf
1eb7411fb0
Merge pull request #76 from YosysHQ/plloutglobal_fix 
Add needed PLLOUTGLOBAL ports and mapped it
 2018-09-25 18:15:00 +02:00
David Shah
f1aa7093fe ice40: Fix carry packer bug 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-25 15:52:32 +01:00
David Shah
dea87e46c4 ice40: LVDS input bitstream support 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-24 17:58:55 +01:00
David Shah
2ee86ab5a8 ice40: Tristate IO support fixes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-24 15:25:37 +01:00
David Shah
d5d9fb27a6 ice40: Validity check for LVDS IO 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-24 15:14:28 +01:00
David Shah
9834b68041 ice40: Remove obsolete belType member 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-24 14:27:50 +01:00
Miodrag Milanovic
f8e258825f Added required checks for PLL and fixed messages eol 2018-09-19 18:41:28 +02:00
Eddie Hung
c9059fc7d0 [ice40] TimingPortClass of LC.O ports without any inputs now TMG_IGNORE 2018-09-15 15:16:21 -07:00
Miodrag Milanovic
fdf7593c42 Add needed PLLOUTGLOBAL ports and mapped it properly 2018-09-12 18:33:08 +02:00
Serge Bazanski
8ed64450f3
Merge pull request #56 from YosysHQ/q3k/issue-55 
ice40: make PLL packing more robust
 2018-08-19 21:37:02 +01:00
Sergiusz Bazanski
1bf22a7f64 ice40: make PLL packing more robust 2018-08-19 21:30:55 +01:00
Clifford Wolf
801f630983 Add more missing iCE40 gfx (LP/HX is complete now) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-19 18:43:38 +02:00
Clifford Wolf
49d3857f97 Add iCE40 gfx for carry chain pips and LUT cascade pips 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-19 17:55:54 +02:00
Clifford Wolf
e45769292a Fix iCE40 pip gfx for pips on the top edge of a switchbox 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-19 17:23:21 +02:00
Clifford Wolf
b7d4c7afd9 Add iCE40 gfx for IO span-4 corners 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-19 16:53:34 +02:00
Clifford Wolf
7cdafb8121 Add iCE40 gfx for span-4 wires between IO tiles 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-19 16:31:02 +02:00
Clifford Wolf
26be6f9761
Merge pull request #47 from YosysHQ/settings_propagate 
Use settings for placer1 and router1
 2018-08-18 19:25:19 +02:00
Clifford Wolf
a346793c19 Add iCE40 gfx for wires connecting fabric tiles and IO tiles 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-18 17:17:01 +02:00
Clifford Wolf
456a83430a Improve iCE40 gfx for IO tiles and RAM tiles 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-18 16:20:33 +02:00
Clifford Wolf
5500cf3aff Add ice40 wire attributes (grid position, segment list) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-18 14:14:27 +02:00
Clifford Wolf
97520bb728 Merge branch 'master' of github.com:YosysHQ/nextpnr into archattr 2018-08-18 13:06:21 +02:00
Miodrag Milanovic
3c51007026 do not break if there are no nets loaded from sym section 2018-08-18 10:28:50 +02:00
Clifford Wolf
428f0b9eba Add Arch attrs API 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-14 17:16:14 +02:00
Eddie Hung
fc0496ec71 Merge remote-tracking branch 'origin/master' into placer_speedup 2018-08-10 19:51:35 -07:00
Eddie Hung
a41500a015 Rework Arch::logicCellsCompatible() to take pointer + size, allowing use of std::array 2018-08-10 19:50:27 -07:00
Miodrag Milanovic
e5006d4f2f Save settings and give nicer names to some 2018-08-10 19:11:30 +02:00
Eddie Hung
396cae5118 Make containers static 2018-08-09 20:53:33 -07:00
Miodrag Milanovic
93a0d24560 Use settings for placer1 and router1 2018-08-09 18:39:10 +02:00
David Shah
ed602baa06
Merge pull request #42 from YosysHQ/floorplan 
Add basic data structures for floorplanning
 2018-08-09 10:49:11 +02:00
Clifford Wolf
5ddde5c49f Add pip locations 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-09 10:39:53 +02:00
Eddie Hung
41e05c95aa ice40: Speedup Arch::predictDelay() with pass-by-ref 2018-08-08 19:52:39 -07:00
Miodrag Milanovic
61bce47f3c Use settings for json and pcf 2018-08-08 20:14:18 +02:00
Clifford Wolf
f6189e4677 Merge branch 'master' of github.com:YosysHQ/nextpnr into constids 2018-08-08 19:35:13 +02:00
David Shah
cd4e761bb7
Merge pull request #44 from YosysHQ/improve_timing_spec 
Speed up budget allocator using topographical ordering and update cell timing API
 2018-08-08 19:23:47 +02:00
Miodrag Milanovic
46aa56021b Moved option to common 2018-08-08 18:34:12 +02:00
Miodrag Milanovic
fc5cee6fb8 clangformat 2018-08-08 18:17:34 +02:00
David Shah
751335977f ice40: Add error for unknown cell type when getting timing info 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 18:07:34 +02:00
Clifford Wolf
f875a37467 Get rid of old iCE40 id_ Arch members 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-08 17:17:16 +02:00
David Shah
433ad6462e Arch API: Removing Arch::isIOCell 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 17:06:59 +02:00
Clifford Wolf
e03ae50e21 Get rid of PortPin and BelType (ice40, generic, docs) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-08 17:01:18 +02:00
David Shah
e6eb203868 ice40: Add timing arcs through global buffers 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 16:34:41 +02:00
David Shah
d173ddba36 timing: Debugging implementation of new timing API 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 15:15:21 +02:00
David Shah
787fe5661c ice40: Timing arch fix 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 15:00:39 +02:00
David Shah
d8b3830031 timing: Update to new use API (currently broken) 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 14:58:43 +02:00
David Shah
bf42e525cb Arch API: New specification for timing port classes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-08 14:37:59 +02:00
Miodrag Milanovic
5df90bc5a5 Merge remote-tracking branch 'origin/master' into common_main 
# Conflicts:
#	ecp5/main.cc
#	ice40/main.cc
 2018-08-08 10:48:05 +02:00
Eddie Hung
f44a5fb904 clangformat 2018-08-06 17:35:23 -07:00
Eddie Hung
1b9a664bb1 Merge branch 'master' into assign_budget_speedup 2018-08-06 12:30:24 -07:00
Eddie Hung
9addcac09c ice40's getBudgetOverride() to return correct delay for different devices 2018-08-06 12:22:13 -07:00
Eddie Hung
21cd1d7dd6 Add new Arch::isIOCell() API function 2018-08-06 12:11:47 -07:00
Miodrag Milanovic
fffaaa613f Added project loader 2018-08-06 19:32:17 +02:00
Eddie Hung
0f3459dbe5 Fix ice40's getBudgetOverride() to override only for COUT -> CIN 2018-08-06 08:22:08 -07:00
Eddie Hung
823ceaacbf Change getBudgetOverride() signature to return bool and modify budget in place 2018-08-06 07:56:28 -07:00
Eddie Hung
f048deb33d Restore initial assign_budget() call after pack(), restrict call after initial_placement to slack_redist 2018-08-05 22:55:58 -07:00
David Shah
1ce0b5add2 API change: Use CellInfo* and NetInfo* as cell/net handles (Python bindings) 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-05 16:21:13 +02:00
Miodrag Milanovic
7794bbfb3f Fix message for pcf loading 2018-08-05 16:13:49 +02:00
Miodrag Milanovic
3bb9a7df01 Added command parser and common implementation 2018-08-05 16:13:34 +02:00
Clifford Wolf
5e53075990 API change: Use CellInfo* and NetInfo* as cell/net handles (common, ice40) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-05 15:25:42 +02:00
Clifford Wolf
287fe7e894 clangformat 2018-08-05 14:18:34 +02:00
Clifford Wolf
528eddcaf7 Fix bug in ice40 estimateDelay() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-04 22:29:43 +02:00
Clifford Wolf
175da732ac Use faster model for ice40 predictDelay() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-04 20:16:43 +02:00
Clifford Wolf
f6b3333a7d Add new iCE40 delay estimator and delay predictor 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-04 19:50:49 +02:00
David Shah
67347573c2 ice40: Bitstream gen for LUT permutation 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-04 18:23:48 +02:00
Clifford Wolf
31fe52581b Add generation of models to tmfuzz 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-04 16:54:12 +02:00
Clifford Wolf
bd36cc1275 Refactor ice40 timing fuzzer used to create delay estimates 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-04 13:41:42 +02:00
Clifford Wolf
700e68746a Fix bug in ice40 chipdby.py add_wire() that moves some wires to X0/Y0 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-04 13:33:24 +02:00
Clifford Wolf
086bc941a8 Remove SVG functionality from ice40 main 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-04 11:52:35 +02:00
Clifford Wolf
96291f17aa Merge branch 'master' of github.com:YosysHQ/nextpnr into lutperm 2018-08-04 10:32:07 +02:00
Eddie Hung
d66edf5223 Merge branch 'master' into slack_redist_freq 2018-08-03 23:43:53 -07:00
David Shah
65d73eb983
Merge pull request #23 from daveshah1/use_placeconstr 
Making use of relative constraints
 2018-08-04 08:32:42 +02:00
David Shah
affc6da1af ice40: Add SB_GB timing to database 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-04 08:28:13 +02:00
David Shah
082b8bf272 clangformat 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-04 08:18:04 +02:00
David Shah
176a23936c Tidy up 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-04 08:15:49 +02:00
Eddie Hung
3d5dcda12c Auto frequency only if --freq 0 is set 2018-08-03 19:53:32 -07:00
Clifford Wolf
8d372b86f3 Proper ice40 wire types 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-03 21:11:12 +02:00
David Shah
b937e6defe Add constraint weight as a command line option 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-03 18:31:54 +02:00
Clifford Wolf
2a1d54389f Add iCE40 pseudo-pips for lut permutation 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-03 17:37:59 +02:00
David Shah
fd2174149c Fixing constraint placement bugs 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-03 16:29:44 +02:00
David Shah
8c518cb838 Fixing relative constraint implementation 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-03 15:40:01 +02:00
David Shah
7e9209878c Reworking packer and placer to use new generic rel legaliser 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-03 15:00:32 +02:00
David Shah
26c68c4bcc Remove old place legaliser, set placement constraints instead (currently ignored by placer) 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-03 13:18:48 +02:00
Clifford Wolf
80e6b17ec9
Merge pull request #21 from daveshah1/promote_logic_globals 
ice40: Promote 'logic' globals as well as clock/enable/reset
 2018-08-03 12:51:55 +02:00
Clifford Wolf
e673d9d2db
Merge pull request #22 from YosysHQ/routethru 
Add iCE40 LUT route-through pips
 2018-08-03 12:51:37 +02:00
David Shah
483f1b772c ice40: Promote 'logic' globals as well as clock/enable/reset 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-03 09:56:56 +02:00
David Shah
35bc80e130 ice40: Add bitstream gen for routethru LUTs 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-03 09:26:37 +02:00
Miodrag Milanovic
a761b772c8 Make worker generic 2018-08-02 18:10:01 +02:00
Miodrag Milanović
e46209e734
Merge pull request #11 from mmicko/project_load 
preserve command line parameters for project load
 2018-08-02 08:24:49 -07:00
Clifford Wolf
36009645ce Add LUT route-through pips to iCE40 architecture database 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-02 16:28:47 +02:00
David Shah
a7269a685e ice40: Use real cell timings 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-02 16:02:51 +02:00
David Shah
c0aaac8dfa ice40: Adding cell timings to chipdb 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-02 15:20:43 +02:00
Clifford Wolf
6ccf8629b5 Add Router1Cfg 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-02 13:58:23 +02:00
Miodrag Milanovic
869a804ee1 preserve command line parameters for project load 2018-08-02 06:29:21 +02:00
Clifford Wolf
29dd98420b Remove getFrameDecal() API 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-01 11:30:11 +02:00
David Shah
0414c93403 ice40: Add HFOSC support, force fabric routing on oscillators for now 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-01 09:45:08 +02:00
David Shah
bbd2ecf558 clangformat 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-01 09:33:52 +02:00
Miodrag Milanovic
009bed51cb Display warning only if gui is not used 2018-08-01 08:26:50 +02:00
Miodrag Milanovic
8293569c32 Fix filenames for MSVC build 2018-08-01 08:16:38 +02:00
David Shah
b1a9978922 Merge branch 'redist_slack' into 'master' 
Update budgets throughout placement and routing

See merge request SymbioticEDA/nextpnr!16
 2018-08-01 05:59:34 +00:00
Eddie Hung
92ec2cd138 clangformat for stuff I've touched 2018-07-31 20:57:36 -07:00
Sergiusz Bazanski
85fc356fc1 clangformat 2018-08-01 03:59:27 +01:00
Eddie Hung
f646ec790a Modify the getNetinfo*() functions and getBudgetOverride() to not use 
user_idx and to take a PortRef& instead
 2018-07-31 19:31:54 -07:00
Eddie Hung
720e815865 Add --slack_redist_iter for ice40 2018-07-31 19:07:39 -07:00
Eddie Hung
5d58d6ad1b Merge branch 'redist_slack' of gitlab.com:SymbioticEDA/nextpnr into redist_slack 2018-07-31 18:26:39 -07:00
Eddie Hung
2d75053744 Merge remote-tracking branch 'origin/estdelay' into redist_slack 
Conflicts:
	ecp5/arch.cc
	generic/arch.cc
	ice40/arch.cc
 2018-07-31 16:18:08 -07:00
Eddie Hung
70747b9355 Merge branch 'redist_slack' into 'redist_slack' 
# Conflicts:
#   common/timing.cc
 2018-07-31 17:51:56 +00:00
Clifford Wolf
41726087b7 getChipName() should be const 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-31 17:01:38 +02:00
Clifford Wolf
2652485a01 Use icestorm timing information 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-31 16:43:19 +02:00
Clifford Wolf
32ff0059fe Add binary search to getBelPinWire() and getBelPinType() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-31 11:55:25 +02:00
Eddie Hung
07e2c9ba99 assign_budget() after initial placement, not after pack 2018-07-30 22:20:49 -07:00
Eddie Hung
a82f6f4105 Modify predictDelay signature 2018-07-30 21:51:30 -07:00
Eddie Hung
a099aca3c2 Modify predictDelay signature 2018-07-30 19:19:30 -07:00
Eddie Hung
d5049bf0ed Merge remote-tracking branch 'origin/estdelay' into redist_slack 2018-07-30 18:59:04 -07:00
Eddie Hung
46b7469652 Merge remote-tracking branch 'origin/master' into redist_slack 2018-07-30 18:14:40 -07:00
Clifford Wolf
b121008372 Towards better ice40 timing data 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-30 17:17:07 +02:00
David Shah
b09183db3b Use DelayInfo for cell timing instead of delay_t 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-30 16:59:30 +02:00
David Shah
84e0082925 cmake: Set --fast and --slow chipdb.py arguments 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-30 16:40:56 +02:00
Clifford Wolf
3d8b0087c3 Add ice40 chipdb.py --fast/--slow 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-30 16:36:34 +02:00
Clifford Wolf
8f9b031ef0 Add iCE40 fast/slow delay fields to chipdb 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-30 16:21:20 +02:00
David Shah
267970c01e ice40: Improving legalisation move statistics 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-30 16:18:49 +02:00
David Shah
edc6cf8b23 ice40: Print legalisation statistics 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-30 16:13:02 +02:00
Clifford Wolf
0daffec2a0 Add predictDelay Arch API 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-30 15:35:40 +02:00
Clifford Wolf
0db86b8619 Improve ice40/benchmark 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-30 13:57:14 +02:00
Eddie Hung
beabb429b0 clangformat 2018-07-28 14:11:43 -07:00
Eddie Hung
02b3bda7f6 ice40 estimateDelay to account for out/in muxes 2018-07-27 19:52:45 -07:00
Eddie Hung
cd561b4316 getBudgetOverride() now handles COUT crossing tiles 2018-07-26 22:30:15 -07:00
Eddie Hung
97e546041e Revert "Remove Arch::getBudgetOverride()" 
This reverts commit 749dae4ae5.
 2018-07-26 21:37:19 -07:00
Eddie Hung
d5c2332ebf Merge remote-tracking branch 'origin/master' into redist_slack 2018-07-26 21:00:26 -07:00
Sergiusz Bazanski
c37d2baaf6 common: rename GraphicElement::{style,type} enums, add _MAX members 2018-07-26 16:39:19 +01:00
Clifford Wolf
03f92948d1 clangformat and GraphicElement::style comments 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-26 17:14:56 +02:00
Clifford Wolf
467e0926f9 Add getWireType()/getPipType() API 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-26 16:38:11 +02:00
Clifford Wolf
6a59b8522c Move iCE40 switchbox gfx to UI groups 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-26 16:21:01 +02:00
Clifford Wolf
7152ae1e3d Add iCE40 pip gfx for carry_in mux 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-26 15:42:32 +02:00
Clifford Wolf
a86c4f2f5d Improvements in bbasm 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-26 15:22:52 +02:00
Eddie Hung
749dae4ae5 Remove Arch::getBudgetOverride() 2018-07-25 23:02:31 -07:00
Eddie Hung
e2f8deec41 clangformat 2018-07-25 18:22:23 -07:00
Eddie Hung
a21cc4dd5b Merge remote-tracking branch 'origin/master' into redist_slack 2018-07-25 17:55:20 -07:00