Commit Graph

18 Commits

Author SHA1 Message Date
Lofty
883f274802 mistral: M10K initialisation support 2022-03-12 17:08:20 +00:00
Lofty
3e688a3ac9 mistral: fixes and debug info 2022-03-09 17:13:54 +00:00
Lofty
33e031a284 mistral: M10K cell function 2022-03-09 17:13:54 +00:00
Lofty
af6735bdf4 mistral: add M10K bel 2022-03-09 17:13:54 +00:00
gatecat
76683a1e3c refactor: Use constids instead of id("..")
Signed-off-by: gatecat <gatecat@ds0.me>
2022-02-16 17:09:54 +00:00
Olivier Galibert
f88c119461 mistral: Add internal oscillator support 2021-10-17 14:26:24 +02:00
Olivier Galibert
bfd61411e7 cyclonev_hps_interface_mpu_general_purpose: Use a id_ identifier 2021-10-15 12:05:24 +02:00
gatecat
f5f7ef6864 mistral: Adding support for MLABs as memory
Signed-off-by: gatecat <gatecat@ds0.me>
2021-10-05 12:40:47 +01:00
gatecat
fe31fba623 mistral: Add bel pins for MLAB write port
Signed-off-by: gatecat <gatecat@ds0.me>
2021-10-03 15:18:41 +01:00
gatecat
9d7f90dd89 mistral: Add MISTRAL_CLKBUF cell type
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 21:28:48 +01:00
gatecat
3bb94192d5 mistral: Tidying up
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 14:54:33 +01:00
gatecat
d39e67da7e mistral: First pass at carry packing
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 14:54:33 +01:00
gatecat
18e05ec852 mistral: Fix constant trimming
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 14:54:33 +01:00
gatecat
ad5e5f80ca mistral: Rename clock buffer primitive
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 14:54:33 +01:00
gatecat
386b5b901c mistral: Implement some misc. things
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 14:54:33 +01:00
gatecat
96f16c8635 mistral: Add a basic QSF parser
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 14:54:33 +01:00
gatecat
595b354184 mistral: Add some packing logic based on nexus
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 14:54:33 +01:00
gatecat
879ac39e53 mistral: Renamed arch from cyclonev
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 14:54:33 +01:00