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Author SHA1 Message Date
Adrien Prost-Boucle
cc04882b17 BaseCtx : Fix crash in getNetByAlias() 2024-10-01 15:24:40 +02:00
gatecat
9b51c6e337 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-30 14:51:33 +02:00
gatecat
fcdaf3f86c Remove fpga_interchange 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-30 13:10:30 +02:00
gatecat
1967db170d xilinx: Support for complex IOLOGIC 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-27 17:37:46 +02:00
gatecat
24fc33c014 xilinx: Basic I/ODDR support 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-27 17:09:15 +02:00
gatecat
d3c0f945da xilinx: Fix BRAM placement, clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-27 16:24:47 +02:00
gatecat
38e5faca85 xilinx: Fix workaround for unsupported xdc construct 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-27 16:07:38 +02:00
gatecat
e4dfd4e622 xilinx: Support single-port LUTRAM variants 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-26 18:11:01 +02:00
gatecat
7516b8950a xilinx: Few more stub timings 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-26 17:30:36 +02:00
gatecat
118ecbc6b3 xilinx: Remove unnecessary assert 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-26 15:58:16 +02:00
gatecat
c90d872e35 xilinx: Filter out another missing pip type 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-26 15:56:20 +02:00
Adrien Prost-Boucle
437fb70ed3 Himbaechel xilinx : Fix packing of cascaded DSP 2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle
cd51a0c2fc Placer : Emit non-fatal error messages before ending the program 2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle
9da05b6001 Himbaechel xilinx : DSP packing : Emit a non-fatal error message 2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle
2031a067a0 Himbaechel xilinx : More flexibility about types of DSP parameters 2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle
81bf92a855 Himbaechel xilinx : DSP packing : Disable clustering 2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle
8a0e062520 Himbaechel xilinx : DSP packing : Improve code efficiency 2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle
a08229d6b6 Placer : Clearer messages in warnings and errors 2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle
9bea22ed1e Himbaechel xilinx : DSP packing : Fix identification of cascaded ports and share identification code 2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle
ad9a54cc69 Himbaechel xilinx : More cascaded input ports for which routing is skipped 2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle
04f5f80766 Himbaechel xilinx : Add safety check in DSP packing for 7-series 2024-09-24 12:06:56 +02:00
Adrien Prost-Boucle
db0c99199e Himbaechel xilinx : Add support of DSP packing for 7-series 2024-09-24 12:06:56 +02:00
Rowan Goemans
bbdf7aacb0 timing_log: warn on min time violation when timing fail is allowed 2024-09-24 08:57:21 +02:00
Rowan Goemans
0af42f1218 common: Use NPNR_ASSERT_FALSE for unreachable case 2024-09-24 08:57:21 +02:00
Rowan Goemans
93e233dad9 timing: Fix hold slack not matching reported path delay 2024-09-24 08:57:21 +02:00
Rowan Goemans
098dcaedec timing: remove the articial clock delay inflation 2024-09-24 08:57:21 +02:00
Rowan Goemans
0fce4b8f4e timing: lower clock_delay_fact to 1 to check if CI passes 2024-09-24 08:57:21 +02:00
Rowan Goemans
25d64b2105 timing_log: Fix logging indendation to match master 
timing: Disable clock_skew analysis by default
 2024-09-24 08:57:21 +02:00
Rowan Goemans
5488cd994b router: Enable clock skew analysis during routing 2024-09-24 08:57:21 +02:00
Rowan Goemans
8ee2c5612c timing: Add safe zero check function for delay_t 2024-09-24 08:57:21 +02:00
Rowan Goemans
a7f79fd681 timing: minor cleanup and stupid mistake fixups 2024-09-24 08:57:21 +02:00
Rowan Goemans
bca6f6394a timing: Fix slack calculations 
timing: Fix max_delay_by_domain_pair function
timing: Fix hold time check
 2024-09-24 08:57:21 +02:00
Rowan Goemans
eb0bf9ea9c report: Handle new segment types 
timing_log: Use common segment type strings
 2024-09-24 08:57:21 +02:00
Rowan Goemans
3b7fec8c4f report: Handle new segment types 2024-09-24 08:57:21 +02:00
Rowan Goemans
4488d42368 log: Remove bad usage of [[no_return]] 2024-09-24 08:57:21 +02:00
Rowan Goemans
8e12dfc693 timing: cleanup clock2clock reporting 
timing: Add clock2clock delay as seperate
        timing line item.
 2024-09-24 08:57:21 +02:00
Rowan Goemans
86106cb49a timing: integrate c2c delays and cleanup code 2024-09-24 08:57:21 +02:00
Rowan Goemans
fc3b2de8da timing: Add clock skew to arrival and required time 2024-09-24 08:57:21 +02:00
Rowan Goemans
60ee682d58 timing: Make hold violations an error 2024-09-24 08:57:21 +02:00
Rowan Goemans
82ea65d984 timing: Report min delay violated in timing logger 2024-09-24 08:57:21 +02:00
Rowan Goemans
7aeed52c06 common: Add some convenience functions for development 2024-09-24 08:57:21 +02:00
Rowan Goemans
c25da06d03 timing: Start identification of min_delay violations 2024-09-24 08:57:21 +02:00
Rowan Goemans
44665a9c4d timing: Allow critical path traversal for shortest paths 2024-09-24 08:57:21 +02:00
Rowan Goemans
2d542eb63a timing: Add hold time to bound of critical path report 2024-09-24 08:57:21 +02:00
gatecat
4b63b1115e Bump tests submodule 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-09-20 13:44:45 +02:00
Jonas Thörnblad
6ca64526bb Fix handling of RNG seed 
* Fix truncation of output seed value from 64 bits to 32 bits (int
  instead of uint64) when written to json file.

* Fix input seed value conversion when --seed option is used.

* Remove input seed value scrambling (use of rngseed()) when --seed
  or --randomize-seed option is used since the output seed value will
  be the scrambled value and not the seed that was actually supplied
  or generated.
 2024-09-18 16:29:32 +02:00
Rowan Goemans
2627d4e0ad
ecp5: Allow disabling of global promotion (#1367) 2024-09-12 20:16:17 +02:00
YRabbit
50bd8d09b0
Gowin. Implement the EMCU primitive. (#1366) 
* Gowin. Implement the EMCU primitive.

Add support for the GW1NSR-4C's embedded Cortex-M3 processor. Since it
uses flash in its own way, we disable additional flash processing for
this case.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Gowin. Fix merge.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

---------

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-09-12 08:53:39 +01:00
YRabbit
ff7b8535bc
Gowin. Add DHCEN primitive. (#1349) 
* Gowin. Add DHCEN primitive.

This primitive allows you to dynamically turn off and turn on the
networks of high-speed clocks.

This is done tracking the routes to the sinks and if the route passes
through a special HCLK MUX (this may be the input MUX or the output MUX,
as well as the interbank MUX), then the control signal of this MUX is
used.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Gowin. Change the DHCEN binding

Use the entire PIP instead of a wire - avoids normalisation and may also
be useful in the future when calculating clock stuff.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

---------

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-09-11 10:18:26 +01:00
Rowan Goemans
8d0f52fbf9
timing: Move towards DelayPairs for timing reporting (#1359) 2024-09-11 07:23:46 +01:00