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Author SHA1 Message Date
Miodrag Milanovic
41914876ef .gitignore for nextpnr-himbaechel 2023-12-23 11:09:26 +01:00
gatecat
56587859d3 nexus: Improve error reporting for illegal carry chains 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-12-22 15:40:29 +01:00
gatecat
535709a9a9 placer1: Fix various bitrot 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-12-13 11:37:30 +01:00
Lofty
d1083fd348 static/ice40: bug fixes for ultraplus 2023-12-13 11:37:20 +01:00
Miodrag Milanovic
b4ca68c8ef Add ability to override Cluster methods in Himbaechel 2023-12-11 13:53:52 +01:00
gatecat
6d9322457e static: Reduce stddev of initial solution 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-26 16:51:47 +01:00
YRabbit
c13b34f20e gowin: Himbaechel. Add BSRAM for all chips. 
The following primitives are implemented for the GW1N-1, GW2A-18,
    GW2AR-18C, GW1NSR-4C, GW1NR-9C, GW1NR-9 and GW1N-4 chips:

    * pROM     - read only memory - (bitwidth: 1, 2, 4, 8, 16, 32).
    * pROMX9   - read only memory - (bitwidth: 9, 18, 36).
    * SDPB     - semidual port    - (bitwidth: 1, 2, 4, 8, 16, 32).
    * SDPX9B   - semidual port    - (bitwidth: 9, 18, 36).
    * DPB      - dual port        - (bitwidth: 16).
    * DPX9B    - dual port        - (bitwidth: 18).
    * SP       - single port      - (bitwidth: 1, 2, 4, 8, 16, 32).
    * SPX9     - single port      - (bitwidth: 9, 18, 36).

    For GW1NSR-4C and GW1NR-9 chips, SP/SPX9 primitives with data widths
    of 32/36 bits are implemented using a pair of 16-bit wide
    primitives.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-11-26 13:08:09 +01:00
YRabbit
90d4863dd4 gowin: Himbaechel. Add GW1NZ-1 BSRAM. 
The following primitives are implemented for the GW1NZ-1 chip:

* pROM     - read only memory - (bitwidth: 1, 2, 4, 8, 16, 32).
* pROMX9   - read only memory - (bitwidth: 9, 18, 36).
* SDPB     - semidual port    - (bitwidth: 1, 2, 4, 8, 16, 32).
* SDPX9B   - semidual port    - (bitwidth: 9, 18, 36).
* DPB      - dual port        - (bitwidth: 16).
* DPX9B    - dual port        - (bitwidth: 18).
* SP       - single port      - (bitwidth: 1, 2, 4, 8, 16, 32).
* SPX9     - single port      - (bitwidth: 9, 18, 36).

Also:
 - The creation of databases for GW1NS-2 has been removed - this was not
   planned to be supported in Himbaechel from the very beginning and
   even examples were not created in apicula for this chip due to the
   lack of boards with it on sale.
 - It is temporarily prohibited to connect DFFs and LUTs into clusters
   because for some reason this prevents the creation of images on lower
   chips (placer cannot find the placement), although without these
   clusters the images are quite working. Requires further research.
 - Added creation of ALU with mode 0 - addition. Such an element is not
   generated by Yosys, but it is a favorite vendor element and its
   support here greatly simplifies the compilation of vendor netlists.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-11-26 13:08:09 +01:00
YRabbit
f2c280feda gowin: Himbaechel. Initial BSRAM support 
Only pROM/pROMX9 for now

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-11-26 13:08:09 +01:00
Miodrag Milanovic
e3f4578b3b CRLF -> LF eol 2023-11-23 09:22:07 +01:00
Miodrag Milanovic
ec60542ffd create wiremap for himbaechel arch 2023-11-23 09:22:07 +01:00
Miodrag Milanovic
1ec8e411d7 set render bound box, so grid is displayed 2023-11-23 08:21:26 +01:00
Miodrag Milanovic
0b8a93eed5 fix compile warning 2023-11-23 08:21:26 +01:00
gatecat
de3d5be8f0 python: Remove deprecated use of Py_SetProgramName 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-23 06:49:15 +01:00
Balint Cristian
7814f44883 Fix abstract class implementation for fpga_interchange 
Signed-off-by: Balint Cristian <cristian.balint@gmail.com>
 2023-11-23 06:49:01 +01:00
gatecat
6683fd4ada himbaechel: Fix when more then 32k unique node shapes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-22 17:11:27 +01:00
gatecat
55635cf2cd Update README 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-17 09:14:19 +01:00
gatecat
e2a887ef0d himbaechel: Switch default back to router1 for now 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-17 09:09:59 +01:00
gatecat
5bfe0dd1b1 himbaechel: Adding a xilinx uarch for xc7 with prjxray 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-14 17:12:09 +01:00
laanwj
a32ad13a86 ecp5: Don't segfault while packing FFs when DI port of TRELLIS_FF unconnected 
Currently a segfault happens when the DI port is not specified. Leaving
it unconnected is probably incorrect, but it shouldn't crash the placer.
Fix by adding a check.
 2023-11-14 11:55:51 +01:00
uis
a4d2244300 Fix printf formats 2023-11-13 13:59:51 +01:00
YRabbit
0106c3d299 gowin: Himbaechel. Diff io BUGFIX. 
Fixed incorrect use of attributes instead of parameters.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-11-13 13:59:28 +01:00
Lofty
506d5f9422 machxo2: less pessimistic delay prediction 2023-11-09 06:48:50 +01:00
gatecat
4c6003ac0b router2: Don't use estimates for constant nets 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-07 15:55:22 +01:00
gatecat
7b0e082000 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-07 09:02:35 +01:00
gatecat
cf647463e4 himbaechel: Add support for new constants API 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-07 09:00:03 +01:00
gatecat
fe52840054 archapi: Add new API for global constant routing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-07 09:00:03 +01:00
Lofty
e3c44dd20a ice40: add IO group to static 2023-11-07 08:18:35 +01:00
Lofty
214cc4315e static: density multiplier should be a vector 2023-11-07 08:18:35 +01:00
Lofty
d6f54fd9df ice40: add static placer support 2023-10-29 08:46:33 +01:00
gatecat
d40c6e850d himbaechel: Generation speedup and improvements 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-10-29 07:46:45 +01:00
gatecat
74d7ebc71f clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-10-28 17:10:42 +02:00
Justin Rajewski
6bae89b8b7 Undid accidental formatting 2023-10-26 21:21:14 +02:00
Justin Rajewski
7cac0249a1 Fixes for building on windows 2023-10-26 21:21:14 +02:00
Justin Rajewski
95f0a19391 Fixes for building on windows 2023-10-26 21:21:14 +02:00
Justin Rajewski
1238b69d74 Fixes for building on windows 2023-10-26 21:21:14 +02:00
gatecat
4a7e58a938 static/ecp5: zero bel area for RAMW because it's a zero-area cell 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-10-14 09:40:41 +02:00
Miodrag Milanovic
5a2eff2120 compile fix 2023-10-09 09:00:27 +02:00
gatecat
0eb9a9ad02 placer_static: Initial prototype 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-10-02 14:56:40 +02:00
Miodrag Milanovic
95e7598cc6 Fix timing lookup for DP8KC 2023-10-02 14:49:17 +02:00
Miodrag Milanovic
e4cb7ea337 proper clock calc due after funcion change 2023-10-02 14:49:17 +02:00
Miodrag Milanovic
f0325730a8 made higher estimate and use proper speed 2023-10-02 14:49:17 +02:00
Miodrag Milanovic
c2e7d3d611 remove commented sections 2023-10-02 14:49:17 +02:00
Miodrag Milanovic
1811c71438 update trellis version 2023-10-02 14:49:17 +02:00
Miodrag Milanovic
1a92c83c3a properly assign latest fuzzed data 2023-10-02 14:49:17 +02:00
Miodrag Milanovic
ed7064b210 select proper signal 2023-10-02 14:49:17 +02:00
Miodrag Milanovic
72546a2186 made delay_t int type 2023-10-02 14:49:17 +02:00
Miodrag Milanovic
657d2898cf import proper data where possible 2023-10-02 14:49:17 +02:00
Miodrag Milanovic
c2b75b355f use timing data 2023-10-02 14:49:17 +02:00
Miodrag Milanovic
40313eacf0 fix import 2023-10-02 14:49:17 +02:00