* Gowin. Add IODELAY.
Input/Output delay (IODELAY) is programmable delay uint in IO block.
This delay line is enabled before/after the IO pad and allows the signal
to be delayed statically or dynamically during 0-127 stages each lasting
from 18 to 30 picoseconds depending on the chip family.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Replacing assertions with log_error.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---------
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Add sampling part to IO blocks (input only). This edge detector will
allow to dynamically adjust DDR decoding window in the future.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. FFs placement.
* Allow clusters to be created from FFs and LUTs;
* Immediately create pass-through LUTs from free LUTs adjacent to FF - at the same time ensure alternating use of LUT inputs;
* In case of constant networks, such pass-through LUTs are disconnected from networks altogether;
* Allow FF to be placed directly into SSRAM slides - this is useful when using synchronous reading.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Fix aux name creation
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Use I3 for pass-trough LUTs
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---------
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Himbaechel Gowin: Add support for CLKDIV and CLKDIV2
* Himbaechel Gowin: Add support for CLKDIV and CLKDIV2
* Gowin Himbaechel: HCLK Bug fixes and corrections
DQCE and DCS primitives are added.
DQCE allows the internal logic to enable or disable the clock network in
the quadrant. When clock network is disabled, all logic drivern by this
clock is no longer toggled, thus reducing the total power consumtion of
the device.
DCS allows you to select one of four sources for two clock wires (6 and 7).
Wires 6 and 7 have not been used up to this point.
Since "hardware" primitives operate strictly in their own quadrants,
user-specified primitives are converted into one or more "hardware"
primitives as needed.
Also:
- minor edits to make the most of helper functions like connectPorts()
- when creating bases, the corresponding constants are assigned to the
VCC and GND wires, but for now huge nodes are used because, for an
unknown reason, the constants mechanism makes large examples
inoperable. So for now we remain on the nodes.
Compatible with older Apicula databases.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
It was not taken into account that there are only 6 ALUs per cell. As a
result, on complex designs where ALUs and LUT-based memory are involved
and there are many LUTs (like in the RISCV emulator), there were
sometimes false positives about placement conflicts.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
As the board on the GW1N-1 chip becomes a rarity, its replacement is the
Tangnano1k board with the GW1NZ-1 chip. This chip has a unique mechanism
for turning off power to important things such as OSC, PLL, etc.
Here we introduce a primitive that allows energy saving to be controlled
dynamically.
We also bring the names of some functions to uniformity.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Add description of BSRAM harness
In some cases, Gowin IDE adds a number of LUTs and DFFs to the BSRAM. Here we are trying to add similar elements.
More details with pictures: https://github.com/YosysHQ/apicula/blob/master/doc/bsram-fix.md
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
For the following primitives:
- PADD9
- PADD18
- MULT9X9
- MULT18X18
- MULT36X36
- MULTALU18X18
- MULTALU36X18
- MULTADDALU18X18
- ALU54D
packing and processing of fixed wires between macro and between DSP
blocks is implemented.
Clusters of DSP and macro blocks are processed using custom placement of
cluster elements.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Corrects the situation when it is impossible to use IOBUF with two
IOLOGIC elements at the same time - input and output.
Addresses https://github.com/YosysHQ/nextpnr/issues/1275
This is done by dividing one IOLOGIC Bel into two - input IOLOGIC and
output IOLOGIC plus checking for compatibility of the cells located
there.
At the moment, this check is simple and allows only the combination of
DDR and DDRC primitives.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
The OCE signal in the SP(X)9B primitive is intended to control the
built-in output register. The documentation states that this port is
invalid when READ_MODE=0 is used. However, it has been experimentally
established that you cannot simply apply VCC or GND to it and forget it
- the discrepancy between the signal on this port and the signal on the
CE port leads to both skipping data reading and unnecessary reading
after CE has switched to 0.
Here we force these ports to be connected to the network, except in the
case where the user controls the OCE signal using non-constant signals.
Also:
* All PIPs for clock spines are made inaccessible to the common router
- in general, using these routes for signals that have not been
processed by a special globals router is fraught with effects that
are difficult to detect.
* The INV primitive has been added purely to speed up development -
this primitive is not generated by Yosys, but is almost always
present in vendor output files.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Information about what function (main or auxiliary) the cell performs in
these primitives is transmitted through the tile's extra data. And this
also allows us to remove the calculation of the coordinates of the
auxiliary cell on the go.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
- experiment with notifyBelChange as an auxiliary cells reservation mechanism;
- since HCLK pips depend on the coordinates, and not on the tile type,
the tile type is copied if necessary;
- information about supported types of differential IO primitives has
been added to the extra information of the chip;
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
To implement unusual IOs that have a dynamically changing configuration
it is convenient to store the switching method in the additional chip
data.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
- minor fixes for pinout saving;
- CST parser taken from generic-based apicula;
- $nextpnr IOB detachment is copied here because it is necessary to copy
attributes from deleted bels.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Shamelessly adapted gatecat's router.
Very early version, not yet puzzled with recognizing clock sources and
controlling the type of wires involved.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
- RAM16SDP1, RAM16SDP2 and RAM16SDP4 support;
- Reading in these primitives is asynchronous, but we have taken
measures so that DFF Bels remain unoccupied and they can be used
to implement synchronous reading.
- misc fixes.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
- Added support for ALU running in "2" ADDSUB mode, the mode that yosys generates for gowin;
- Supports specifying an arbitrary input carry as well as passing the output carry to logic;
- A small restructuring of the source files.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
- MUX2_LUT5, MUX2_LUT6, MUX2_LUT7 and MUX2_LUT8 support;
- storing a common class of files in extra_data;
- misc fixes.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Himbaechel-gowin has learned how to place DFFs of all types by tracking
the compatibility of CLK, CE and LSR inputs, as well as placing mutually
compatible flip-flops in adjacent slices.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
- VSS and VCC sources in each cell are used;
- constant LUT inputs are disabled;
- putting the class declaration into a header file.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
- wires, nodes and whites are generated from bases - apicula;
- roting of SN and EW bidirectional wires is supported;
- supports "wrapping" the wires at the edges of the chip;
- LUT1-4 and two types of DFF(R) are supported;
- simple IO is supported.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
