caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
2,304 Commits 22 Branches 7 Tags 17 MiB
0392cd3a5b
Commit Graph

104 Commits

Author SHA1 Message Date
David Shah
bff7d673ed ice40: Packer and bitstream gen support for MAC16s 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-19 14:03:48 +02:00
David Shah
d221e90706 Reducing performance cost of asserts 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-19 11:43:10 +02:00
David Shah
ddd94edfe0 ice40: Fixes for inverted clocks 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-18 14:01:19 +02:00
David Shah
c75a924c3f ice40: Assign ArchArgs after packing 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-18 12:12:05 +02:00
Sergiusz Bazanski
d327a0afbb Revert "Make ice40::Arch thread-safe" 
This reverts commit 0816f447b7.
 2018-07-14 19:01:33 +01:00
Sergiusz Bazanski
2233040201 Revert "Remove legacy access to state via Arch" 
This reverts commit 18b4b31678.
 2018-07-14 18:50:15 +01:00
Sergiusz Bazanski
18b4b31678 Remove legacy access to state via Arch 2018-07-14 12:02:28 +01:00
Sergiusz Bazanski
0816f447b7 Make ice40::Arch thread-safe 
We move all non-chip data to be private and guard them with an R/W
mutex.

We then modify all calls that access these fields to lock/shared_lock
the mutex as required.

Profiling the code before and after is an exercise left to the reader
:).
 2018-07-13 12:35:39 +01:00
Clifford Wolf
b8a42ff53b Updates from clang-format 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-12 22:04:13 +02:00
David Shah
2e8c0c872f Add NPNR_ASSERT_FALSE, use in bitstream.cc 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-04 13:04:31 +02:00
David Shah
e0a851976f refactor: Replace assert with NPNR_ASSERT 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-04 12:15:23 +02:00
Miodrag Milanovic
1cf8293019 Fixed macros and includes for MSVC 2018-07-03 08:53:44 +02:00
David Shah
302ccc14cf ice40: UltraPlus SPRAM working 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-29 19:58:08 +02:00
David Shah
66670831b8 ice40: PLace legaliser produces a design that is at least routable for picosoc 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-28 16:31:52 +02:00
David Shah
841d126672 CarryInSet added to bitstream gen, add counter tb 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-26 16:04:10 +02:00
David Shah
ded9df61dc Working on debugging carry packer 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-26 13:08:28 +02:00
Miodrag Milanovic
db890d3a81 nets and cells are unique_ptr's 2018-06-25 21:33:48 +02:00
David Shah
1e8840b0f9 Update from increased clangformat line length 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-23 16:12:52 +02:00
Clifford Wolf
746d63f9fa Refactoring bind/unbind API 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-23 15:16:24 +02:00
David Shah
2e6916ecab ice40: Fix UltraPlus quasi-logic-cell bits 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-23 11:25:32 +02:00
Miodrag Milanovic
cb92c10b99 Cleanup almost all deprecation warnings 2018-06-23 09:42:48 +02:00
David Shah
8850f86a8a ice40: SB_LFOSC support, fabric routing only 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-22 19:21:39 +02:00
David Shah
60e885d342 ice40: Adding extra cell wires to database; SB_WARMBOOT working 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-22 18:35:08 +02:00
David Shah
cf78f1b0e4 ice40: Add UltraPlus tiles to database 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-22 16:40:22 +02:00
Clifford Wolf
aa81f9d648 Switched from clifford@clifford.at to clifford@symbioticeda.com for copyright headers 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-22 16:19:17 +02:00
David Shah
71176ac538 Fixing 5k bitstream gen and place heuristics 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-22 12:34:42 +02:00
Clifford Wolf
79d1075345 Getting rid of old IdString API users, Add ctx to many internal APIs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-18 17:08:35 +02:00
Clifford Wolf
8ee149f4fc Rename Design to Context, derive from Arch instead of instantiating 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-18 14:06:37 +02:00
Clifford Wolf
ad18cdb087 Rename Chip to Arch and ChipArgs to ArchArgs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-18 13:35:25 +02:00
Clifford Wolf
4fe8ba5e9a Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into chipdbng 2018-06-17 16:14:58 +02:00
Clifford Wolf
19b665177e Move top-level ChipInfoPOD into ice40 chipdb blob 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-17 16:12:52 +02:00
Clifford Wolf
f38c5660cb Move BitstreamInfoPOD to ice40 chipdb blob 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-17 15:39:19 +02:00
David Shah
f723aaa373 ice40: Fixing negative clock bitstream generation 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-17 15:21:35 +02:00
Clifford Wolf
c0a2f0b89f Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into chipdbng 2018-06-17 14:31:43 +02:00
Clifford Wolf
84defd3fee Minor refactoring of BinaryBlobAssembler, fix alignments 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-17 13:32:38 +02:00
David Shah
1b077320dc General reformatting 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-17 12:53:39 +02:00
David Shah
12818fb694 ice40: Add symbol output to bitstream generation 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-17 12:38:21 +02:00
David Shah
6a937e0b45 Updating copyrights 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-17 11:49:57 +02:00
Clifford Wolf
69e5bc5030 Progress with chipdb refactoring 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-16 19:25:37 +02:00
Clifford Wolf
fe47e7fc2d Update clangformat 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-16 15:25:33 +02:00
David Shah
f079e0d204 ice40: Fix BRAM initialisation 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-16 14:44:10 +02:00
David Shah
c9a784ec0c ice40: Include RAM init data in bitstream 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-16 14:44:10 +02:00
David Shah
04f1d7516a ice40: Fix bitstream generation when parameters are unspecified 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-16 14:44:10 +02:00
David Shah
23b1fc02fb ice40: Bitstream generation for RAM 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-16 14:44:10 +02:00
Clifford Wolf
391d49c13e Add nextpnr namespace 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-12 14:24:59 +02:00
Clifford Wolf
ac67482380 Remove pool, dict, vector namespace aliases 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-11 19:56:33 +02:00
David Shah
d3f1112580 Improving 5k support 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-10 17:20:29 +02:00
Clifford Wolf
602e6fab1e Add support for iCE40 global buffers (currently only for 1k devices) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-10 16:31:06 +02:00
David Shah
02b83d6db6 Debugging on icebreaker 2018-06-10 15:06:26 +02:00
David Shah
8d5da98122 ice40: Set config bits for unused IO 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-10 13:38:34 +02:00
David Shah
30e672313d ice40: Add IO config to bitstream 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-10 13:24:48 +02:00
David Shah
d0bd657551 ice40: Write logic cell config to bitstream 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-10 12:58:05 +02:00
David Shah
827a43c88c ice40: Start adding routing to asc output 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-10 12:11:58 +02:00
David Shah
d0431225f1 ice40: Writing an empty ASC file 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-10 11:56:07 +02:00