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Author SHA1 Message Date
gatecat
8c85e648df
Merge pull request #639 from litghost/parameter_iteration 
Update parameter processing based on new DeviceResources metadata
 2021-03-23 16:51:28 +00:00
Keith Rothman
720f64ea60 [FPGA interchange] Add support for global buffers from chipdb. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-23 09:41:45 -07:00
Keith Rothman
0dd93035e4 [FPGA interchange] Convert some string constants to IdString. 
Also add some optional diagnostic prints for cell -> BEL pin mapping.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-23 09:38:37 -07:00
gatecat
b7bf2c706f
Merge pull request #642 from YosysHQ/gatecat/missing-cell-pin 
interchange: Add nice error for missing cell pins
 2021-03-23 16:34:10 +00:00
Keith Rothman
831b94cdac Initial version of inverter logic. 
For now just implements some inspection capabilities, and the site
router (for now) avoids inverted paths.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-23 09:03:07 -07:00
Keith Rothman
ae71206e1f Update FPGA interchange chipdb to v4 with inverter data. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-23 09:01:45 -07:00
Keith Rothman
8a50b02b9b Use new parameter definition data in FPGA interchange processing. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-23 09:01:43 -07:00
Keith Rothman
af1fba9f52 Update latest version of FPGA interchange schema. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-23 09:00:58 -07:00
gatecat
4d8dcab1d3
Merge pull request #641 from litghost/initial_lookahead 
Initial lookahead for FPGA interchange.
 2021-03-23 16:00:17 +00:00
gatecat
79400756f5 interchange: Add nice error for missing cell pins 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-23 15:40:34 +00:00
Keith Rothman
8d1eb0a195 Initial lookahead for FPGA interchange. 
Currently the lookahead is disabled by default because of the time to
compute and RAM usage.  However it does appear to work reasonably well
in testing.  Further effort is required to lower RAM usage after initial
computation, and explore trade-off for cheaper time to compute.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-23 08:16:50 -07:00
gatecat
9ef412c2cc
Merge pull request #638 from litghost/fixup_physical_netlist_writer 
Correct some bugs in writing of physical netlist w.r.t. site sources.
 2021-03-22 18:32:26 +00:00
gatecat
a3ed97c0db
Merge pull request #637 from litghost/refine_site_router 
Refine site router
 2021-03-22 18:32:04 +00:00
gatecat
e8d36bf5bd
Merge pull request #634 from litghost/add_get_bel_pin_type 
Add getBelPinType to Python interface.
 2021-03-22 18:31:48 +00:00
gatecat
f6ae068cb2
Merge pull request #632 from litghost/add_check_pip_for_net 
Add "checkPipAvailForNet" to Arch API.
 2021-03-22 18:31:32 +00:00
Keith Rothman
32f2ec86c4 Rework FPGA interchange site router. 
The new site router should be robust to most situations, and isn't
significantly slower with the use of caching.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-22 09:54:49 -07:00
Keith Rothman
0f4014615c Add missing dependencies to CMake targets. 
- Add additional targets useful for various situations.
 - Have counter test use common remap.v file.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-22 09:47:33 -07:00
Keith Rothman
06bcde6243 Correct some bugs in writing of physical netlist w.r.t. site sources. 
Local site sources should have their driving BEL pin included in the net
so that the site wire is driven by an output BEL pin.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-22 09:46:43 -07:00
Keith Rothman
4cd74bba2c Add getBelPinType to Python interface. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-22 09:25:45 -07:00
Keith Rothman
e7d81913a4 Add "checkPipAvailForNet" to Arch API. 
This is important for distiguishing valid pseudo pips in the FPGA
interchange arch. This also avoids a double or triple lookup of
pip->net map.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-22 09:17:55 -07:00
gatecat
53ed6979a9
Merge pull request #636 from litghost/add_pseudo_pip_data 
Add pseudo pip data
 2021-03-22 15:24:36 +00:00
Keith Rothman
694f9ec3a5 Increment required python-fpga-interchange version. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-22 09:33:12 +00:00
Keith Rothman
db12a83ced Add pseudo pip data to chipdb (with schema bump). 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-22 09:33:12 +00:00
gatecat
68ca923bfe
Merge pull request #635 from litghost/refactor_headers 
Refactor header structures in FPGA interchange Arch.
 2021-03-22 09:30:38 +00:00
Keith Rothman
22c6754bcd Update tests to include Tcl header order fix. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-19 21:36:17 -07:00
Keith Rothman
2cd5bacca0 Refactor header structures in FPGA interchange Arch. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-19 21:36:06 -07:00
gatecat
f52b522964
Merge pull request #633 from YosysHQ/gatecat/optional-ipo 
cmake: Use IPO only if supported
 2021-03-19 10:38:12 +00:00
gatecat
bac2a8ba02 cmake: Use IPO only if supported 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-19 09:40:27 +00:00
gatecat
aa8b12db6f
Merge pull request #631 from litghost/fixup_gui_dependencies 
Update root CMake with some additional features
 2021-03-18 22:02:37 +00:00
gatecat
bc3fe7d014
Merge pull request #630 from litghost/run_clangformat 
Run "make clangformat" to fix up master.
 2021-03-18 21:38:02 +00:00
Keith Rothman
76c6e1248c Add option to link against "libprofiler". 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-18 14:02:07 -07:00
Keith Rothman
d5021e7ed5 Add IPO support for nextpnr, and have it enabled by default. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-18 14:01:40 -07:00
Keith Rothman
f4dc67879e Fixup GUI link dependencies on headers from libraries. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-18 14:00:19 -07:00
Keith Rothman
a3dd5b33bc Run "make clangformat". to fix up master. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-18 13:30:37 -07:00
gatecat
b8678e778e
Merge pull request #629 from litghost/move_hash_selection_to_header 
Moving hash map/set type selection to header.
 2021-03-18 08:14:16 +00:00
Keith Rothman
965ba00e0f Moving hash map/set type selection to header. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-03-17 16:54:29 -07:00
gatecat
5feea4497f
Merge pull request #619 from acomodi/add-cmake-infra-fpga-interchange 
Add CMake infrastructure for fpga interchange
 2021-03-17 14:05:49 +00:00
Alessandro Comodi
01a95faf21 fpga_interchange: temporarily disable failing test 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-17 10:32:35 +01:00
Alessandro Comodi
f6583f7ecc fpga_interchange: minor fixes and comments addition 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-16 22:59:20 +01:00
Alessandro Comodi
c1e668f823 fpga_interchange: address review comments 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-16 22:02:06 +01:00
Alessandro Comodi
f9e9fadbc8 github-actions: use capnp v0.8.0 
This also updates the note in the README for the FPGA interchange

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-16 16:57:07 +01:00
Alessandro Comodi
83544cdf6a github-actions: pin python-fpga-interchange to tag 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-16 16:34:27 +01:00
Alessandro Comodi
c68dfb09c4 github-actions: add basic CI to test FPGA interchange 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-16 15:39:02 +01:00
Alessandro Comodi
f63a9a48a4 fpga_interchange: re-add README with updated instructions 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-16 15:39:02 +01:00
Alessandro Comodi
f52b5b39ed fpga_interchange: tests: add techmap optional source file 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-16 15:39:02 +01:00
Alessandro Comodi
3f3cabea2d fpga_interchange: add bbasm step and archcheck 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-16 15:39:02 +01:00
Alessandro Comodi
0b62e540a3 fpga_interchange: address review comments 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-16 15:39:02 +01:00
Alessandro Comodi
bd2da27e4e fpga_interchange: tests: added comment and fixed XDC 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-16 15:39:02 +01:00
Alessandro Comodi
e5cc03965e fpga_interchange: chipdb: use generic patching function 
Also moved the RapidWright invocation script path under a CMake variable

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-16 15:39:02 +01:00
Alessandro Comodi
490fdb0a1c fpga_interchange: cmake: generate only one device family 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-16 15:39:01 +01:00