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044c9ba2d4
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Author SHA1 Message Date
Maciej Kurc
044c9ba2d4 LUT mapping cache optimizations 1 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-07-16 13:28:40 +02:00
Maciej Kurc
d52516756c Working site LUT mapping cache 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-07-16 12:51:28 +02:00
gatecat
c696e88573
Merge pull request #751 from trabucayre/gw1ns-2 
add support for GW1NS-2 family
 2021-07-06 15:17:41 +01:00
gatecat
bf542f07b0
Merge pull request #754 from YosysHQ/gatecat/ecp5-dcs 
ecp5: Add DCSC support
 2021-07-06 14:06:31 +01:00
Gwenhael Goavec-Merou
027d54e771 .cirrus/Dockerfile.ubuntu20.04: update apycula to 0.0.1a9 2021-07-06 14:34:33 +02:00
gatecat
5b2db015a9
Merge pull request #752 from YosysHQ/gatecat/du-mem-error 
design_utils: Fix memory error
 2021-07-06 12:43:48 +01:00
gatecat
81c549549d ecp5: Add DCSC support 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-06 11:45:37 +01:00
gatecat
c0bb2fb76a
Merge pull request #750 from YosysHQ/gatecat/io-improve 
IO improvements for OBUFTDS
 2021-07-06 11:43:24 +01:00
gatecat
3d0facf119 design_utils: Fix memory error 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-06 11:35:27 +01:00
Gwenhael Goavec-Merou
96263058c3 add support for GW1NS-2 family 
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
 2021-07-06 11:40:41 +02:00
gatecat
31abefc8e4 interchange: Allow pseudo pip wires to overlap with bound site wires on the same net 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-06 10:38:08 +01:00
gatecat
6fe071ad1d router2: Dump pre-bound routes when routing fails in debug mode 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-06 10:21:31 +01:00
gatecat
f64d06fa02 interchange: Improve search for PAD-attached bels 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-06 10:13:50 +01:00
Alessandro Comodi
6edc11de4d interchange: tests: add obuftds test 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-07-06 09:57:26 +01:00
gatecat
8a9fb81036
Merge pull request #748 from acomodi/fix-phys-net-writing 
interchange: phys: skip only nets writing on disconnected out ports
 2021-07-02 18:34:46 +01:00
Alessandro Comodi
888a2462af interchange: phys: skip only nets writing on disconnected out ports 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-07-02 16:12:53 +02:00
gatecat
fe38e70dc1
Merge pull request #747 from cr1901/machxo2 
MachXO2 Checkpoint 1
 2021-07-01 20:17:02 +01:00
gatecat
55c663f7ac
Merge pull request #746 from YosysHQ/gatecat/ic-can-invert-const 
interchange: Handle canInvert PIPs when processing preferred constants
 2021-07-01 15:28:24 +01:00
gatecat
344cfe6216
Merge pull request #745 from YosysHQ/gatecat/ic-node-source 
interchange: Handle case where routing source is a node
 2021-07-01 15:28:16 +01:00
William D. Jones
41d09f7187 machxo2: Fix packing for directly-connected DFFs. 2021-07-01 09:59:53 -04:00
William D. Jones
e625876949 machxo2: Add VHDL primitives, demo, and script. 2021-07-01 09:36:03 -04:00
William D. Jones
45c33e9dcf machxo2: Add a special case for pips whose config bits are in multiple 
tiles.
 2021-07-01 09:36:02 -04:00
William D. Jones
ec239c8c35 machxo2: Hardcode a rule for emitting U_/D_ or G_ prefixes in ASCII output. 2021-07-01 09:36:01 -04:00
William D. Jones
b1f25d4b33 machxo2: Set Pip and Wire delays to reasonable fake values mirroring 
estimateDelay.
 2021-07-01 09:36:00 -04:00
gatecat
74ffe2c543 interchange: Handle canInvert PIPs when processing preferred constants 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-01 13:47:02 +01:00
gatecat
f17643bc08 interchange: Handle case where routing source is a node 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-01 13:19:10 +01:00
gatecat
86bc708299 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-01 13:18:34 +01:00
gatecat
ddff2e2e5e
Merge pull request #744 from YosysHQ/gatecat/const-in-macro 
interchange: Fix handling of constants in macros
 2021-07-01 13:12:38 +01:00
gatecat
79ab283890
Merge pull request #743 from YosysHQ/gatecat/site-rsv-ports 
interchange: Reserve site ports only reachable from dedicated routing
 2021-07-01 13:12:29 +01:00
gatecat
8b4e880827
Merge pull request #742 from acomodi/interchange-do-not-output-zero-user-nets 
interchange: phys: do not output nets which have no users
 2021-07-01 13:12:19 +01:00
gatecat
006a40a353 interchange: Fix handling of constants in macros 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-01 11:45:23 +01:00
Alessandro Comodi
dd7cfccbae interchange: phys: do not output nets which have no users 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-07-01 12:36:05 +02:00
gatecat
523ffbaa37 interchange: Reserve site ports only reachable from dedicated routing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-01 11:28:12 +01:00
gatecat
2124da44d8
Merge pull request #741 from acomodi/fix-ded-interc 
interchange: fix dedicated interconnect exploration
 2021-06-30 20:09:52 +01:00
Alessandro Comodi
cfbd1dfa4d interchange: fix dedicated interconnect exploration 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-30 20:04:23 +02:00
gatecat
152c41c3ac
Merge pull request #739 from YosysHQ/gatecat/usp-io-macro 
interchange: Place entire IO macro based on routeability
 2021-06-30 13:00:12 +01:00
gatecat
b3882f8324 interchange: Fix dedicated interconnect check when site is the same 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-30 11:48:51 +01:00
gatecat
ef18590043 interchange: Place IO macro content based on routing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-30 11:37:30 +01:00
gatecat
91b998bb11
Merge pull request #738 from YosysHQ/json_load_reinit 
Preserve ArchArgs and reinit Context when applicable in GUI, fixes  #737
 2021-06-30 09:59:38 +01:00
Miodrag Milanovic
5c6b8a5f04 Preserve ArchArgs and reinit Context when applicable in GUI 2021-06-30 10:10:18 +02:00
Miodrag Milanovic
6c23fe202c loading json should be disabled in this place 2021-06-30 09:46:25 +02:00
gatecat
2476f116bb interchange: Track the macros that cells have been expanded from 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-29 14:48:47 +01:00
gatecat
78c965141f
Merge pull request #736 from YosysHQ/gatecat/pp-multi-output 
interchange: Allow site wires driven by more than one bel
 2021-06-28 16:27:04 +01:00
gatecat
7115dd3393
Merge pull request #735 from YosysHQ/gatecat/ic-disconn-belpin 
interchange: Handle disconnected bel pins in dedicated interconnect
 2021-06-28 16:26:53 +01:00
gatecat
65a4bce9ad interchange: Allow site wires driven by more than one bel 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-28 14:55:56 +01:00
gatecat
980a7013d2 interchange: Handle disconnected bel pins in dedicated interconnect 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-28 14:45:27 +01:00
gatecat
454617f0cb
Merge pull request #734 from acomodi/remove-rw-patch 
ci: remove RapidWright patching
 2021-06-24 08:27:47 +01:00
Alessandro Comodi
721e760f1a ci: remove RapidWright patching 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-24 08:23:59 +02:00
gatecat
c73d4cf6dd
Merge pull request #733 from acomodi/interchange-move-macro-before-io 
interchange: arch: move macro expansion step before ios packing
 2021-06-18 19:09:18 +01:00
Alessandro Comodi
0344fdcf8d interchange: arch: move macro expansion step before ios packing 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-18 16:42:05 +02:00