Eddie Hung
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04c08b7bc6
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clangformat and more cleanup
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2019-01-10 15:04:51 -08:00 |
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Eddie Hung
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fa3d366ddb
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Add missing operator needed by router_improve
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2018-11-13 10:10:57 -08:00 |
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Eddie Hung
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ca7eef26ac
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Wires now encapsulate segments
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2018-09-02 16:57:11 -07:00 |
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Eddie Hung
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17918b5992
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Fix for multiple id_SLICE_LUT6 per actual SLICE
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2018-08-17 23:05:12 -07:00 |
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Eddie Hung
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7b15569c69
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Use general pin names for QUARTER_SLICE
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2018-08-12 20:29:04 -07:00 |
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Eddie Hung
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56b7299cca
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{SLICEL,SLICEM} -> QUARTER_SLICE
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2018-08-12 20:21:03 -07:00 |
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Eddie Hung
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57c273898c
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Finishes placement now
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2018-08-11 22:24:13 -07:00 |
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Eddie Hung
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8cddc49abc
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Starts placement onto all Xilinx sites
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2018-08-11 18:52:48 -07:00 |
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Eddie Hung
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d53658a079
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Copy ice40 into xc7
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2018-08-11 14:35:49 -07:00 |
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