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Author SHA1 Message Date
Keith Rothman
0758f68020 Update archapi.md with latest signature. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:08:59 -08:00
Keith Rothman
423a10bc31 Change CellInfo in getBelPinsForCellPin to be const. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:08:54 -08:00
gatecat
85af066d4f
Merge pull request #594 from YosysHQ/gatecat/heap-tidying 
Tidying up HeAP
 2021-02-23 21:53:00 +00:00
gatecat
162793aa87 Refactor some common code to CellInfo methods 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-23 13:11:10 +00:00
gatecat
72b7a2e107 HeAP: Document legalise_placement_strict better 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-23 13:11:10 +00:00
gatecat
20f0ba9526 nexus: Fix getPipDelay returning negative after refactor 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-23 12:21:55 +00:00
gatecat
3b45174375 pyconsole: Avoid lockup when reading from stdin 
Create an empty temporary file for stdin; so reads fail rather than
locking up (otherwise doing help() would be enough to completely lock up
the GUI).

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-22 10:48:21 +00:00
gatecat
c0a7cff304 Demote the 'no clocks' warning to info and make clearer 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-20 20:15:52 +00:00
gatecat
6672f17d0a
Merge pull request #592 from YosysHQ/gatecat/rework-delay 
Replace DelayInfo with DelayPair and DelayQuad
 2021-02-20 10:51:57 +00:00
gatecat
e571c707b5 Update generic.md 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-20 10:51:30 +00:00
gatecat
130c5cc768 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-19 13:52:06 +00:00
gatecat
8ab36b4a05 python: Bindings for DelayPair and DelayQuad 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-19 13:41:40 +00:00
gatecat
7922b3bfc4 Replace DelayInfo with DelayPair/DelayQuad 
This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.

This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.

While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-19 11:31:33 +00:00
gatecat
8376db94a7 Add DelayPair and DelayQuad structures 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-19 10:58:16 +00:00
gatecat
5dcb59b13d
Merge pull request #576 from litghost/add_cell_bel_pin_mapping 
Complete FPGA interchange Arch to the point where it can route a wire
 2021-02-19 08:41:58 +00:00
Keith Rothman
c21e23b3eb Fix sign mismatch. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-18 14:08:22 -08:00
Keith Rothman
e138a6c56d Do some spell checking on site_router.cc 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-18 13:34:06 -08:00
Keith Rothman
4766e889c0 Add some utility methods for site instance access. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-18 13:26:52 -08:00
Keith Rothman
532954847a Update README's with latest instructions and features. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-18 13:01:42 -08:00
gatecat
b4a97efe4d
Merge pull request #588 from YosysHQ/gatecat/gowin-fixes 
Gowin regression fixes
 2021-02-18 11:05:04 +00:00
gatecat
cbff1e1371
Merge pull request #590 from cbalint13/master 
Expose ice40 arch placer-heap internal parameters.
 2021-02-18 10:47:39 +00:00
Balint Cristian
456688a49d Expose ice40 arch placer-heap internal parameters. 2021-02-18 00:06:23 +02:00
Keith Rothman
7ecfd98b2d Update tests library to include Bits unit test. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:35 -08:00
Keith Rothman
8ef5411f70 Add utility targets for getting plain text outputs. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:17 -08:00
Keith Rothman
b3dcc9d507 Add IOSTANDARD to ports. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:17 -08:00
Keith Rothman
5833c90210 Emit fixed attributes to output physical netlist. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:17 -08:00
Keith Rothman
8f668f06ca Use Bits library for bit instrisics. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:17 -08:00
Keith Rothman
558a753d3d Refactor "get only from iterator" to a utility. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:17 -08:00
Keith Rothman
9e0ca72827 Keep all build artifacts under create_bba/build. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:16 -08:00
Keith Rothman
f9bd692f75 Change how package pin IO sites are selected. 
The first site type that matches is now selected, under the premise that
the early site types are more general.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:16 -08:00
Keith Rothman
cc687b3b72 Change makefiles to build a FPGA interchange BBA. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:16 -08:00
Keith Rothman
5a7f83c705 Add examples invoking FPGA interchange nextpnr. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:16 -08:00
Keith Rothman
7c1544f4d8 Continue fixes. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:16 -08:00
Keith Rothman
6f1c835221 Disable traversal limit when reading logical netlist. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:16 -08:00
Keith Rothman
c385321248 Add initial site router. 
This site router likely cannot handle the full problem space.  It may
need to be replaced with a more generalize approach as testing
continues.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:16 -08:00
Keith Rothman
a7421399f7 Working on standing up initial constraints system. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:16 -08:00
gatecat
f6dc2dd198 Bump tests submodule to include bits tests 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-17 20:02:33 +00:00
gatecat
782747cc0c
Merge pull request #589 from litghost/add_bits_library 
Add a Bits utility library.
 2021-02-17 20:01:24 +00:00
Keith Rothman
e189666a2d Add a Bits utility library. 
This library captures use of __builtin_popcount and __builtin_ctz on
GCC/clang and hopefully handles the MSVC case.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 11:00:39 -08:00
gatecat
a8c55728e2 gowin: Fix archcheck errors and add to CI 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-17 16:03:03 +00:00
gatecat
18113ff43d gowin: Use base bel bucket/cell type methods 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-17 15:58:00 +00:00
gatecat
09535a95ca gowin: Fix IdStrings being overwritten by wireToGlobal 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-17 15:57:31 +00:00
gatecat
cb957795a3 Update docs/archapi.md 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-17 11:25:53 +00:00
gatecat
d83259828e
Merge pull request #587 from YosysHQ/gatecat/generic-vcc 
generic: Don't generate Vcc if not needed
 2021-02-17 11:17:25 +00:00
gatecat
399c24c805 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-17 10:45:23 +00:00
gatecat
6b4bd0993f generic: Don't generate Vcc if not needed 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-17 10:24:06 +00:00
gatecat
da1ecf0813
Merge pull request #586 from litghost/add_cell_bel_mapping_only 
Add Cell -> BEL Pin maps to FPGA interchange arch.
 2021-02-17 10:16:45 +00:00
gatecat
a77ceec5cf
Merge pull request #585 from YosysHQ/gatecat/remove-ivbfc 
Remove isValidBelForCell
 2021-02-17 08:50:31 +00:00
Keith Rothman
26a187e5eb Require --package when arch BBA contains multiple packages. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-16 14:00:01 -08:00
Keith Rothman
bb4fa7af5b [FPGA Interchange] Add Cell -> BEL Pin maps. 
This also expands the FPGA interchange Arch BBA to include placement
constraints, but doesn't implement them yet.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-16 09:37:19 -08:00