Commit Graph

988 Commits

Author SHA1 Message Date
Keith Rothman
0afa0da19f Add absl::flat_hash_map.
This lowers the CPU cost of using the flat wire map in router2, and should
use less memory as well.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-01 09:55:54 -08:00
Keith Rothman
c65ba121e0 Prevent trival misplacements in placer1.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-26 10:59:48 -08:00
gatecat
b64f45a8ba Remove unused advanced timing constraint API
This API was simply an attractive nuisance as no code was ever developed
to actually process timing constraints (other than clock constraints
which use a different API).

While I do want to consider basic false path support, among other
things, in the near future; I plan for this to use a new API that
doesn't add complexity to the BaseCtx/Context monstrosity and that is
easier to use on the timing analysis side.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-26 10:07:00 +00:00
Keith Rothman
c64a910151 Allow router2 to use routed but not fixed arcs.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-25 15:55:29 -08:00
gatecat
23413a4d12 Fix compiler warnings introduced by -Wextra
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-25 15:15:25 +00:00
gatecat
ab8dfcfba4
Merge pull request #591 from litghost/add_constant_network
Add constant network support to FPGA interchange arch
2021-02-25 10:22:45 +00:00
gatecat
e2cdaa653c
Merge pull request #597 from litghost/add_dynamic_bitarray
Add dynamic bitarray to common library.
2021-02-24 18:22:16 +00:00
Keith Rothman
6d193ffd8b Fix some bugs found in review.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-24 09:09:06 -08:00
Keith Rothman
3650294e51 Add dynamic bitarray to common library.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 15:43:47 -08:00
gatecat
19ae97afd1
Merge pull request #595 from litghost/const_cell_info
Change CellInfo in getBelPinsForCellPin to be const.
2021-02-23 22:55:09 +00:00
gatecat
5de1978632
Merge pull request #596 from litghost/make_clang_format
Run "make clangformat" to fix formatting in new Bits library.
2021-02-23 22:49:35 +00:00
Keith Rothman
5c6e231412 Remove some signedness warnings.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:28 -08:00
Keith Rothman
423a10bc31 Change CellInfo in getBelPinsForCellPin to be const.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:08:54 -08:00
Keith Rothman
bf458cbc5a Run "make clangformat" to fix new Bits library.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 13:55:05 -08:00
gatecat
162793aa87 Refactor some common code to CellInfo methods
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-23 13:11:10 +00:00
gatecat
72b7a2e107 HeAP: Document legalise_placement_strict better
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-23 13:11:10 +00:00
gatecat
c0a7cff304 Demote the 'no clocks' warning to info and make clearer
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-20 20:15:52 +00:00
gatecat
6672f17d0a
Merge pull request #592 from YosysHQ/gatecat/rework-delay
Replace DelayInfo with DelayPair and DelayQuad
2021-02-20 10:51:57 +00:00
gatecat
130c5cc768 clangformat
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-19 13:52:06 +00:00
gatecat
8ab36b4a05 python: Bindings for DelayPair and DelayQuad
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-19 13:41:40 +00:00
gatecat
7922b3bfc4 Replace DelayInfo with DelayPair/DelayQuad
This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.

This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.

While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-19 11:31:33 +00:00
gatecat
8376db94a7 Add DelayPair and DelayQuad structures
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-19 10:58:16 +00:00
gatecat
5dcb59b13d
Merge pull request #576 from litghost/add_cell_bel_pin_mapping
Complete FPGA interchange Arch to the point where it can route a wire
2021-02-19 08:41:58 +00:00
Balint Cristian
456688a49d Expose ice40 arch placer-heap internal parameters. 2021-02-18 00:06:23 +02:00
Keith Rothman
8f668f06ca Use Bits library for bit instrisics.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-17 12:03:17 -08:00
Keith Rothman
558a753d3d Refactor "get only from iterator" to a utility.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-17 12:03:17 -08:00
Keith Rothman
a7421399f7 Working on standing up initial constraints system.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-17 12:03:16 -08:00
Keith Rothman
e189666a2d Add a Bits utility library.
This library captures use of __builtin_popcount and __builtin_ctz on
GCC/clang and hopefully handles the MSVC case.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-17 11:00:39 -08:00
gatecat
c7c13cd95f Remove isValidBelForCell
This Arch API dates from when we were first working out how to
implement placement validity checking, and in practice is little used by
the core parts of placer1/HeAP and the Arch implementation involves a
lot of duplication with isBelLocationValid.

In the short term; placement validity checking is better served by the
combination of checkBelAvail and isValidBelForCellType before placement;
followed by isBelLocationValid after placement (potentially after
moving/swapping multiple cells).

Longer term, removing this API makes things a bit cleaner for a new
validity checking API.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-16 13:31:36 +00:00
gatecat
1b6cdce925
Merge pull request #575 from YosysHQ/gatecat/belpin-2
Support for cell pin to bel pin mappings
2021-02-15 09:38:22 +00:00
gatecat
cede682585
Merge pull request #579 from litghost/add_control_for_split_io
Add control to whether GenericFrontend splits IO ports.
2021-02-12 18:22:06 +00:00
gatecat
c956cae824 Make BaseArch getDecalGraphics return an empty range
Fix assertion failure when opening the GUI on an arch without any
decals.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-12 10:35:51 +00:00
gatecat
ad7bb51030
Merge pull request #580 from litghost/add_design_loaded_state_variable
Add design_loaded state variable.
2021-02-12 09:54:15 +00:00
Keith Rothman
99e397000c Add getBelHidden and add some missing "override" statements.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-11 14:58:02 -08:00
Keith Rothman
96293ab25e Add design_loaded state variable.
This is to decouple the command line flag "--json" and enable other
frontend's.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-11 13:43:23 -08:00
Keith Rothman
73710416b4 Add control to whether GenericFrontend splits IO ports.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-11 13:33:55 -08:00
gatecat
7c7d69e1d2 router2: Support for multiple bel pins per cell pin
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-10 15:14:44 +00:00
gatecat
7dafc64f78 router1: Support for multiple bel pins per cell pin
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-10 14:46:03 +00:00
gatecat
535723f414 Start making use of getBelPinsForCellPin API
This replaces getNetinfoSinkWire with 3 new functions for different use
cases.

At the moment all existing code has been moved to getNetinfoSinkWire
with phys_idx=0 so the build doesn't break; but this won't yet function
properly with more than one sink. But it provides a base on which to
work on refactoring the routers to support this case.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-10 14:18:12 +00:00
gatecat
85bb108ba4 Add getBelPinsForCellPin to Arch API
This is a basic implementation, without considering "M of N"
arrangements (e.g. for LUT permuation where you only want to route to 1
out of 4/6 sinks) or using a type other than IdString to identify bel
pins.

But this is also enough to start working out where in nextpnr will break
due to removing the 1:1 cell:bel pin cardinality, as a next step.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-10 11:54:54 +00:00
gatecat
6bd3dba1e3 Remove the unused CellInfo::pins field
No arches ever actually used this to implement a Cell->Bel pin mapping,
and in practice if any did try they would inevitably hit bitrot.

This field had limited use in practice as it is necessary to also
support cases where one cell pin maps to more than one bel pin. Removing
this old field is the first step towards developing a new API for this.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-10 10:42:26 +00:00
gatecat
11db5a2f1d Add BaseArchRanges for default ArchRanges types
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-09 10:39:14 +00:00
gatecat
2932dc3985 Make BaseCtx destructor virtual
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-08 17:03:22 +00:00
D. Shah
efca63862c Use 'T' postfix to disambiguate LHS and RHS of using
Arches might otherwise have range types named ambigiously with the entry
in ArchRanges.

Signed-off-by: D. Shah <dave@ds0.me>
2021-02-08 10:29:50 +00:00
D. Shah
3e631fe2f4 Add archArgs and archArgsToId to Arch API
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-05 19:19:17 +00:00
D. Shah
59c3db46ca ice40: Switch to BaseArch
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-05 19:19:17 +00:00
D. Shah
a8a27299ae Add pure-virtual ArchAPI interface
This splits out the pure-virtual definition of the architecture API into
ArchAPI; leaving BaseArch to only provide default implementations (which
can now be completely opted out of by deriving from ArchAPI instead of
BaseArch).

Signed-off-by: D. Shah <dave@ds0.me>
2021-02-05 19:19:17 +00:00
D. Shah
b4227f586c Rename ArchBase to BaseArch for consistency with BaseCtx
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-05 19:19:17 +00:00
D. Shah
297cd026b9 Add default implementation of bel bucket functions
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-05 19:19:17 +00:00
D. Shah
ed8e3c83d9 Add default implementation of some range-returning functions
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-05 19:19:17 +00:00