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90 Commits

Author SHA1 Message Date
gatecat
23413a4d12 Fix compiler warnings introduced by -Wextra 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-25 15:15:25 +00:00
gatecat
7922b3bfc4 Replace DelayInfo with DelayPair/DelayQuad 
This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.

This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.

While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-19 11:31:33 +00:00
gatecat
c7c13cd95f Remove isValidBelForCell 
This Arch API dates from when we were first working out how to
implement placement validity checking, and in practice is little used by
the core parts of placer1/HeAP and the Arch implementation involves a
lot of duplication with isBelLocationValid.

In the short term; placement validity checking is better served by the
combination of checkBelAvail and isValidBelForCellType before placement;
followed by isBelLocationValid after placement (potentially after
moving/swapping multiple cells).

Longer term, removing this API makes things a bit cleaner for a new
validity checking API.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-16 13:31:36 +00:00
gatecat
6de733b38c machxo2: Misc tidying up 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-12 10:43:15 +00:00
gatecat
33eca9a3d2 machxo2: Python bindings and stub GUI 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-12 10:40:03 +00:00
gatecat
8f5133d811 machxo2: Use snake_case for non-ArchAPI functions 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-12 10:36:59 +00:00
gatecat
b539363cd0 machxo2: Use IdStringLists in earnest 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-12 10:36:59 +00:00
gatecat
3f7618283d machxo2: Update with Arch API changes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-12 10:36:59 +00:00
William D. Jones
32433db7ae machxo2: Prepare README.md for first PR. 2021-02-12 10:36:59 +00:00
William D. Jones
3dbd5b0932 machxo2: Add prefix parameter to simtest.sh. Remove show command from 
simtest.sh. Update README.md.
 2021-02-12 10:36:59 +00:00
William D. Jones
730e543ca6 machxo2: Add prefix parameter to simple.sh. Update README.md. 2021-02-12 10:36:59 +00:00
William D. Jones
0b0faa2f1c machxo2: Fill in more about mitertest.sh in README.md and clean up a bit. 2021-02-12 10:36:59 +00:00
William D. Jones
73c851d8e0 machxo2: Add two new examples: blinky_ext and aforementioned UART. 2021-02-12 10:36:59 +00:00
William D. Jones
74b5e846a5 machxo2: auto-top does not work for smt miter either. 2021-02-12 10:36:59 +00:00
William D. Jones
77bb3e73cd machxo2: Fix unhelpful comment in mitertest.sh. 2021-02-12 10:36:59 +00:00
William D. Jones
2b54e87548 machxo2: Verilog examples using OSCH cannot be simulated in mitertest.sh. Remove show from mitertest.sh. 2021-02-12 10:36:59 +00:00
William D. Jones
a3a38b0536 machxo2: Add prefix parameter to mitertest.sh. All Verilog files top modules named "top". 2021-02-12 10:36:59 +00:00
William D. Jones
0aa472fb3a machxo2: Add prefix paramter to demo.sh. 2021-02-12 10:36:59 +00:00
mtnrbq
b9eb443e54 Add demo with RGB LED 2021-02-12 10:36:59 +00:00
William D. Jones
4948e8d914 machxo2: Fix packing when FF is driven by a constant; UART test core working on silicon, fails post-synth sim. 2021-02-12 10:36:59 +00:00
William D. Jones
086bca18b8 machxo2: Add packing logic to handle FFs fed with constant value; UART test core routes. 2021-02-12 10:36:59 +00:00
William D. Jones
3ab300a28e machxo2: Add additional packing phase to pack remaining FFs. 2021-02-12 10:36:59 +00:00
William D. Jones
f18df5ed59 machxo2: Don't write out config bits for cells without location info. 2021-02-12 10:36:59 +00:00
William D. Jones
da1b15d6f5 machxo2: Special-case left and right I/O wire names in ASCII generation. 2021-02-12 10:36:59 +00:00
William D. Jones
8629d7b692 machxo2: Add quickstart README.md. 2021-02-12 10:36:59 +00:00
William D. Jones
07bc6bac53 machxo2: Fail CMake configuration is BUILD_PYTHON is ON (not supported for now). 2021-02-12 10:36:59 +00:00
William D. Jones
c9487293e9 machxo2: Fix REGMODE identifier (per slice, not per-FF). 2021-02-12 10:36:59 +00:00
William D. Jones
d0b822c036 machxo2: Add demo.sh TinyFPGA Ax example. 2021-02-12 10:36:59 +00:00
William D. Jones
0250aaaddd machxo2: clang format. 2021-02-12 10:36:59 +00:00
William D. Jones
2c9d4ba9ae machxo2: Fix reversed interpretation of REG_SD config bits. 2021-02-12 10:36:59 +00:00
William D. Jones
0d00c10e2f machxo2: Add bitstream generation for OSCH. 2021-02-12 10:36:59 +00:00
William D. Jones
884e7d9a98 machxo2: Add basic bitstream generation for PIC tiles and I/O. 2021-02-12 10:36:59 +00:00
William D. Jones
d485dc6ef6 machxo2: Add REGMODE to bitstream output. 2021-02-12 10:36:59 +00:00
William D. Jones
5415194b39 machxo2: Checkpoint commit for slice bitstream generation. 2021-02-12 10:36:59 +00:00
William D. Jones
cf2db7a4c4 machxo2: Write out pips to bitstream. 2021-02-12 10:36:59 +00:00
William D. Jones
56656b2b24 machxo2: Emit empty bitstream file. 2021-02-12 10:36:59 +00:00
William D. Jones
695fb7e569 machxo2: Add/fix copyright banners. 2021-02-12 10:36:59 +00:00
William D. Jones
75f33e0c55 machxo2: Add stub bitstream writer plus support files. 2021-02-12 10:36:59 +00:00
William D. Jones
e1f72318e0 machxo2: Tweak A-star parameters for acceptable performance. 2021-02-12 10:36:59 +00:00
William D. Jones
447b3a060c machxo2: Fix getWireName. 2021-02-12 10:36:59 +00:00
William D. Jones
385917059b machxo2: Fix typos where absolute positions were treated as relative. 2021-02-12 10:36:59 +00:00
William D. Jones
722d1f2542 machxo2: Finish implementing Wire API functions. nextpnr segfaults on example with constraints. 2021-02-12 10:36:59 +00:00
William D. Jones
861c12e6eb machxo2: Finish implementing Pip API functions. 2021-02-12 10:36:59 +00:00
William D. Jones
0adde4aede machxo2: Implement 4 more Wire/Pip API functions. 2021-02-12 10:36:59 +00:00
William D. Jones
19a9554bda machxo2: Add stub getAttrs API functions. 2021-02-12 10:36:59 +00:00
William D. Jones
9a9054188c machxo2: Implement getByName/getName for Wires and Pips. 2021-02-12 10:36:59 +00:00
William D. Jones
e4a6fd3571 machxo2: Convert facade_import to use pybind API from pytrellis. 2021-02-12 10:36:59 +00:00
William D. Jones
31ea8f8719 machxo2: Use attrmvcp in yosys to implement LOC constraint and only check for LOC on FACADE_IO. 2021-02-12 10:36:59 +00:00
William D. Jones
9c37aef499 machxo2: Detect LOC attributes during packing to implement rudimentary user constraints. 2021-02-12 10:36:59 +00:00
William D. Jones
0e63178fe1 machxo2: clang format. 2021-02-12 10:36:59 +00:00