Until a comprehensive clock router is developed, the order in which
private cases are handled is important.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Uses the information of the special input pins for the PLL in the
current chip. If such pins are involved, no routing is performed and
information about the use of implicit wires is passed to the packer.
The RESET and RESET_P inputs are now also disabled if they are connected
to VSS/VCC.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Includes information on additional pin functions such as RPLL_C_IN, GCLKC_3, SCLK and others.
This allows a decision to be made about special network routing of such pins
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
The rPLL primitive for the simplest chip (GW1N-1) in the family is
processed. All parameters of the primitive are passed on to gowin_pack,
and general-purpose wires are used for routing outputs of the primitive.
Compatible with older versions of apicula, but in this case will refuse
to place the new primitive.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
There is no need to multiply item names, it is a rudiment of my very
first addition to nextpnr.
Fully compatible with older versions of Apicula.
Note: the cosmetic changes in lines with RAM are not my initiative, but
the result of applying clang-format.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Refactor in order to detect networks that will be routed in a special
mode earlier. This makes it possible to mark the source of such networks
as a global buffer, thereby removing their influence on element
placement.
In addition, timing classes are set for some cells.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
A simple router that takes advantage of the fact that in each cell with
DFFs their CLK inputs can directly connect to the global clock network.
Networks with a large number of such sinks are sought and then each
network is assigned to the available independent global clock networks.
There are limited possibilities for routing mixed networks, that is,
when the sinks are not only CLKs: in this case an attempt is made to use
wires such as SN10/20 and EW10/20, that is, one short transition can be
added between the global clock network and the sink.
* At this time, networks with a source other than the I/O pin are not
supported. This is typical for Tangnano4k and runber boards.
* Router is disabled by default, you need to specify option
--enable-globals to activate
* No new chip bases are required. This may change in the distant future.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
In the Gowin chips, the tiles are connected to each other by a one-hop
wire, among others. There are 4 one-hop wires, of which 2 are shared
between north/south and east/west, have three names: e.g. SN10 and N110
and S110.
But only one of them, the first, occurs as a sink for PIP, that is, you
can not get a route that would pass through the S110 for example.
This commit corrects the names to SN?0 and EW?0 at the wire creation
stage to avoid dead wires.
In addition, the SN?0 and EW?0 are among the few sinks for global clock
wires and now there is the possibility of a more optimal clock routing.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Gowin chips have a highly sophisticated system of long wires that are
wired to each cell and allow the clock or logic to spread quickly.
This commit implements some of the capabilities of the long wire system
for quadrants, leaving out the fine-tuning of them for each column.
To make use of the long wire system, the specified wire is cut at the
driver and a special cell is placed between the driver and the rest of
the wire.
* VCC and GND can not use long wires because they are in every cell and
there is no point in using a net
* Long wire numbers can be specified manually or assigned automatically.
* The route from the driver to the port of the new cell can be quite
long, this will have to be solved somehow.
* It might make sense to add a mechanism for automatically finding
candidates for long wires.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Only the recognition of the directive in the .CST file and elementary
checks are added, but not the long-wire mechanism itself.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
This chip has a different default state for one type of I/O buffer ---
you have to explicitly switch it to the normal state by feeding VCC/VSS
to certain inputs.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Compatible with older versions of apicula bases.
Also small fixes and as the number of virtual Bels grows it is necessary
to assign them Z coordinate in a centralized way to avoid conflicts and
for this purpose introduced the BelZ enum.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
GSR is added automatically if it was not instantiated by the user explicitly.
Compatible with old apicula bases, the functionality does not work, but
the crash does not happen --- just a warning.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
For differential signals it is necessary to set the position of two pins
at once: P and N.
This commit adds that capability and also adds another style of location
setting --- with the pin letter in square brackets used in vendor tools.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Items such as LUT, DFF, MUX, ALU, IOB are displayed;
* Local wires, 1-2-4-8 wires are displayed;
* The clock spines, taps and branches are displayed with some caveats.
For now, you can not create a project in the GUI because of possible
conflict with another PR (about GW1NR-9C support), but you can specify
the board in the command line and load .JSON and .CST in the GUI.
Although ALUs are displayed, but the CIN and COUT wires are not. This is
still an unsolved problem.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Some models have I/O cells that are IOBUFs, and other types (IBUFs and
OBUFs) are obtained by feeding 1 or 0 to the OEN input. This is done
with general-purpose routing so it's best to do it here to avoid
conflicts.
For this purpose, in the new bases, these special cells are of type IOBS
(IOB Simplified).
The proposed changes are compatible with bases of previous versions of
Apycula and do not require changing .CST constraint files.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
This makes predictDelay be based on an arbitrary belpin pair rather
than a arc of a net based on cell placement. This way 'what-if'
decisions can be evaluated without actually changing placement;
potentially useful for parallel placement.
A new helper predictArcDelay behaves like the old predictDelay to
minimise the impact on existing passes; only arches need be updated.
Signed-off-by: gatecat <gatecat@ds0.me>
Instead of parsing the partnumber with a regular expression,
a simple table is used. This is done because the structure
of the partnumber changes as new features appear (e.g., ES instead of C6/I5)
This commit does not yet disable the very first regular expression check.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* A hardwired MUX within each logical cell is used.
* The delay is equal 0.
* No user placement constraints.
* The output route contains dummy PIPs. They are ignored by gowin_pack, but it may be worth removing them.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
