caiyu/nextpnr
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109 Commits

Author SHA1 Message Date
D. Shah
c10238de8c ice40: Switch from RelPtr to RelSlice 
This replaces RelPtrs and a separate length field with a Rust-style
slice containing both a pointer and a length; with bounds checking
always enforced.

Thus iterating over these structures is both cleaner and safer.

Signed-off-by: D. Shah <dave@ds0.me>
 2021-01-27 18:35:49 +00:00
Miodrag Milanovic
2726f3af91 Fixes for new part types 2020-07-08 16:45:27 +02:00
Sylvain Munaut
9b71bba747 ice40: Add fallback behavior for Extra Cell config bits vectors 
This helps make new nextpnr compatible with old chipdbs when a parameters
goes from single bit to multi bit.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2020-06-02 20:21:16 +02:00
Sylvain Munaut
5e2b6bcef9 ice40: Add support for the 2nd bit of SHIFTREG_DIV_MODE 
This requires the matching chipdb update from icestorm project !

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2020-06-02 11:03:04 +02:00
David Shah
dd7f7a53bd ice40: Improve error handling of Lattice-style parameters 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-10 15:28:16 +00:00
David Shah
1839a3a770 Major Property improvements for common and iCE40 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-05 14:52:15 +01:00
David Shah
fa77a5ae4a clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-24 11:43:01 +01:00
Simon Schubert
88eeafae12 ice40: add RGB_DRV/LED_DRV_CUR support for u4k 2019-06-10 14:04:25 +02:00
Sylvain Munaut
d401e3e1a0 ice40: Add support for SB_I2C and SB_SPI 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-03-25 23:48:59 +01:00
Simon Schubert
7044f56246 ice40: support u4k 2019-02-23 17:39:20 +01:00
David Shah
953a3ac552 ice40: Add PCF support for -pullup, -pullup_resistor and -nowarn 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-12-20 20:52:54 +00:00
David Shah
e7fc42ac84 ice40: Improve bitstream error handling 
Fixes #161 and provides a clearer error for #170

Signed-off-by: David Shah <dave@ds0.me>
 2018-12-06 11:19:48 +00:00
David Shah
88e1e6bdf4 clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-06 10:52:46 +00:00
Daniel Serpell
d4b3c1d819 ice40: Add support for placing SB_LEDDA_IP block. 
Signed-off-by: Daniel Serpell <daniel.serpell@gmail.com>
 2018-12-01 22:27:04 -03:00
Sylvain Munaut
5f0f2b060b ice40: Update the way LVDS inputs are handled during bitstream generation 
* Instead of "patching" input_en, we completely separate config for
   normal and LVDS pair.
   - For normal pair, nothing changes
   - For LVDS pairs, the IE/REN bits are always set as if the input buffer
     are disabled. Then if input_en was set to 1 (i.e. the input is
     actually for something), then we set the IoCtrl.LVDS bit.
   - Also for LVDS, if input is used, pullups are forcibly disabled.

 * When scanning for unused IOs, never process those part of a LVDS pair.
   They will have been configured by the complement

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-28 16:04:23 +01:00
Sylvain Munaut
e8556aff37 ice40: Add support for SB_RGBA_DRV 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
519d4e2af8 ice40: Add support for SB_GB_IO 
During packing we replace them by standard SB_IO cells and create the
'fake' SB_GB that matches that IO site global buffer connection.

It's done in a separate pass because we need to make sure the nextpnr iob
have been dealt first so we have our final Bel location on the SB_IO.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
d8e4c21d96 ice40: Add support for PLL global outputs via PADIN 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
bc9f2da470 ice40: Introduce the concept of forPadIn SB_GB 
Those are cells that are created mainly to handle the various sources a
global network can be driven from other than a user net.

When the flag is set, this means the global network usually driven by
this BEL is in fact driven by something else and so that SB_GB BEL and
matching global network can't be used.

This is also what gets used to set the extra bits during bitstream
generation.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut
42fbb110fc ice40/bitstream: Handle IoCtrl.IE_ polarity when configuring unused SB_IO 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 13:12:43 +01:00
Sylvain Munaut
01950a2349 ice40/bitstream: Convert to UNIX line endings 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-16 16:24:56 +01:00
David Shah
20aa0a0eed ice40: Remove unnecessary RAM assertion 
Fixes #121

Signed-off-by: David Shah <dave@ds0.me>
 2018-11-16 13:18:53 +00:00
David Shah
becf3021bd ice40: Don't set colbuf bits for 384 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-11-11 23:52:04 +01:00
David Shah
ea03aafc26 clangformat 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-30 15:13:18 +01:00
David Shah
dea87e46c4 ice40: LVDS input bitstream support 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-24 17:58:55 +01:00
Miodrag Milanovic
3c51007026 do not break if there are no nets loaded from sym section 2018-08-18 10:28:50 +02:00
Clifford Wolf
e03ae50e21 Get rid of PortPin and BelType (ice40, generic, docs) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-08 17:01:18 +02:00
Clifford Wolf
5e53075990 API change: Use CellInfo* and NetInfo* as cell/net handles (common, ice40) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-05 15:25:42 +02:00
Clifford Wolf
287fe7e894 clangformat 2018-08-05 14:18:34 +02:00
David Shah
67347573c2 ice40: Bitstream gen for LUT permutation 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-04 18:23:48 +02:00
David Shah
35bc80e130 ice40: Add bitstream gen for routethru LUTs 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-03 09:26:37 +02:00
David Shah
0414c93403 ice40: Add HFOSC support, force fabric routing on oscillators for now 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-01 09:45:08 +02:00
Sergiusz Bazanski
85fc356fc1 clangformat 2018-08-01 03:59:27 +01:00
Eddie Hung
950f33c1bb clangformat 2018-07-25 17:53:01 -07:00
Sergiusz Bazanski
90ba958abe ice40: fixes before review 2018-07-24 03:19:22 +01:00
Sergiusz Bazanski
eaae1d299c ice40: move PLL->IO from pseudo pip to second uphill bel 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
65ceb20784 ice40: emit list of upbels in chipdb 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
fae7994bc3 clang-format 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
dbf79d78bb ice40: A slightly nicer way to do this. 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
e6c7b14465 ice40: Refactor PLL/LOCK LUT splicing out into Arch:: 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski
2b1f7875bb ice40: Implement emitting PLLs 2018-07-24 02:38:10 +01:00
David Shah
bfa1137fe0 clangformat 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-23 13:02:57 +02:00
Miodrag Milanovic
b9c413a5aa Move to new API and remove deprecated 2018-07-22 19:58:17 +02:00
Clifford Wolf
62b66e0208 Rename getWireBelPin to getBelPinWire 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-22 10:59:21 +02:00
Miodrag Milanovic
f438fc615b Added driver and users for nets 2018-07-21 20:21:48 +02:00
Miodrag Milanovic
3175891cb5 Map ports to nets 2018-07-21 19:48:00 +02:00
Miodrag Milanovic
57c63e6921 create io cells out of asc 2018-07-21 17:54:35 +02:00
Miodrag Milanovic
912a79dc33 add cells that are in default state or no configuration 2018-07-21 17:38:22 +02:00
Miodrag Milanovic
7beb4739d4 Add used cells and attach them to bels 2018-07-21 17:04:47 +02:00
Miodrag Milanovic
13339c0355 Assign proper pips 2018-07-21 15:08:49 +02:00