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Author SHA1 Message Date
YRabbit
cc273c1257 gowin: Himbaechel. Handle SDP OCE 
Semi-dual port BSRAM (in Gowin terminology) has the same feature as
Single Port - the CE and OCE signals must be synchronized.

Such a sin has not yet been noticed for Dual Port.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-02-09 08:04:08 +01:00
YRabbit
833cb86b51 gowin: Himbaechel. Edit message text. 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-02-09 08:03:56 +01:00
YRabbit
4eeb56c0e0 gowin: Himbaechel. Improve global router. 
* Don't stop at the first bad "arc", but use the global network to the
  maximum.
* Report partial/full use of global wires for the network.
* In case of complete routing failure, releasing the source - this is
  actually a BUGFIX.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-02-09 08:03:56 +01:00
YRabbit
b05cb86291 gowin: Himbaechel. Global router BUGFIX. 
Ignore networks without users.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-01-29 13:18:24 +01:00
Miodrag Milanovic
a65ddff8ba Update workflows 2024-01-29 10:37:55 +01:00
YRabbit
325985e055 gowin: Himbaechel. SPX9 BSRAM BUGFIX. 
This type setting is not needed here - the packer distinguishes memory
features by the X9 attribute, which will be correct anyway.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-01-27 15:05:58 +01:00
gatecat
e7192cd375 static: Fix ifdefs 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-01-26 17:57:22 +01:00
gatecat
9dcd0eff16 static: Add a basic threadpool 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-01-25 08:24:41 +01:00
YRabbit
73b7de74a5 gowin: Himbaechel. Fix the style. 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-01-23 14:00:29 +01:00
YRabbit
91b0c4f90a gowin: Himbaechel. Deal with SP BSRAM ports. 
The OCE signal in the SP(X)9B primitive is intended to control the
built-in output register. The documentation states that this port is
invalid when READ_MODE=0 is used. However, it has been experimentally
established that you cannot simply apply VCC or GND to it and forget it
- the discrepancy between the signal on this port and the signal on the
CE port leads to both skipping data reading and unnecessary reading
after CE has switched to 0.
Here we force these ports to be connected to the network, except in the
case where the user controls the OCE signal using non-constant signals.

Also:
  * All PIPs for clock spines are made inaccessible to the common router
    - in general, using these routes for signals that have not been
    processed by a special globals router is fraught with effects that
    are difficult to detect.
  * The INV primitive has been added purely to speed up development -
    this primitive is not generated by Yosys, but is almost always
    present in vendor output files.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-01-23 14:00:29 +01:00
Pepijn de Vos
97f5c3ca2c Add documentation for Himbaechel Gowin uarch 2024-01-23 12:17:01 +01:00
gatecat
8968c84ce6 Increase the set of PnR-excluded cells 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-01-23 12:16:14 +01:00
gatecat
4220ce1007 gui: Remove const on max_elems_ 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-01-18 15:34:40 +01:00
Lofty
a0e360fd9f rust: convert netinfo_driver to Option 2024-01-18 14:07:23 +01:00
Lofty
14a09061a5 rust: rework portref_cell 2024-01-18 14:07:23 +01:00
Lofty
dfd651a132 rust: fix some calls that got wrongly replaced 2024-01-18 14:07:23 +01:00
Lofty
d0e01661a5 rust: fix build error 2024-01-18 14:07:23 +01:00
Lofty
6e4e81429c rust: nets isn't send/sync 2024-01-18 14:07:23 +01:00
Lofty
c8e1cbc5f2 rust: transform pointers to references where possible 2024-01-18 14:07:23 +01:00
Lofty
c5fc34f11a rust: slight cleanup 2024-01-18 14:07:23 +01:00
Lofty
f12e76479c rust: add mutex for arch manipulation 2024-01-18 14:07:23 +01:00
gatecat
2afb1f632e clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-01-12 10:09:28 +01:00
gatecat
d00fdc8f7a frontend: Ignore $scopeinfo 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-01-11 15:48:53 +01:00
Lofty
257fbe549d readme: update build prerequisites 2024-01-05 20:12:05 +00:00
Lofty
d557e3e35f hashlib: constify const_iterators 2024-01-04 17:32:56 +01:00
Lofty
2c8ad5fa1d Fix a renamed Qt item 2024-01-04 17:32:56 +01:00
Lofty
d867019dcb upgrade to C++17 2024-01-04 17:32:56 +01:00
gatecat
5013392841 Add trivially copyable invariant for ID types 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-01-04 17:04:28 +01:00
dragonmux
6a9ad61051 rust: Fixed an unused parameter warning 2024-01-04 10:39:45 +01:00
dragonmux
cb269b46d6 rust: Made the wrap helper inline and fixed an accidental copy error 2024-01-04 10:39:45 +01:00
dragonmux
3e46fbc655 rust: Reworked the unwrap helpers by effectively hiding the crime of memcpy()'ing into a non-POD type from the compiler 
There is still the possibility that this can explode horribly, but the result should be the same codegen and fixes the warning

This also makes the helpers `inline` so they'll usually be compiled out for a nice speed boost
 2024-01-04 10:39:45 +01:00
dragonmux
cfeb588d32 rust: Reworked npnr_context_get_pips_leak() using std::accumulate() and fixed an accidental copy problem 2024-01-04 10:39:45 +01:00
dragonmux
7d0c4eaf1b rust: Reworked npnr_context_get_wires_leak() using std::accumulate() and fixed an accidental copy problem 2024-01-04 10:39:45 +01:00
dragonmux
e9c69ac00c gui: Fixed unused parameters and spurious ; warnings in one of the headers 2024-01-04 10:39:45 +01:00
dragonmux
cb4db2d368 ice40: Fixed unused parameters and spurious ; warnings in some of the headers 2024-01-04 10:39:45 +01:00
dragonmux
7fd80c5a92 common/kernel: Fixed unused parameters and spurious ; warnings in some of the headers 2024-01-04 10:39:45 +01:00
Lofty
50d43742ce rust: silence warnings 2024-01-03 14:51:33 +01:00
gatecat
e12ab86c75 rust: Fix segfault 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-01-03 13:42:18 +01:00
Lofty
1bbcc5f2c4 (broken) third round of review fixes 2024-01-03 13:42:18 +01:00
Lofty
49d505831d second round of review fixes 2024-01-03 13:42:18 +01:00
Lofty
1dbd81067a first round of review fixes 2024-01-03 13:42:18 +01:00
Lofty
d2297b1ba0 Add Rust FFI bindings 2024-01-03 13:42:18 +01:00
gatecat
4a4025192a run clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-12-26 09:54:34 +01:00
Miodrag Milanovic
41914876ef .gitignore for nextpnr-himbaechel 2023-12-23 11:09:26 +01:00
gatecat
56587859d3 nexus: Improve error reporting for illegal carry chains 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-12-22 15:40:29 +01:00
gatecat
535709a9a9 placer1: Fix various bitrot 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-12-13 11:37:30 +01:00
Lofty
d1083fd348 static/ice40: bug fixes for ultraplus 2023-12-13 11:37:20 +01:00
Miodrag Milanovic
b4ca68c8ef Add ability to override Cluster methods in Himbaechel 2023-12-11 13:53:52 +01:00
gatecat
6d9322457e static: Reduce stddev of initial solution 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-26 16:51:47 +01:00
YRabbit
c13b34f20e gowin: Himbaechel. Add BSRAM for all chips. 
The following primitives are implemented for the GW1N-1, GW2A-18,
    GW2AR-18C, GW1NSR-4C, GW1NR-9C, GW1NR-9 and GW1N-4 chips:

    * pROM     - read only memory - (bitwidth: 1, 2, 4, 8, 16, 32).
    * pROMX9   - read only memory - (bitwidth: 9, 18, 36).
    * SDPB     - semidual port    - (bitwidth: 1, 2, 4, 8, 16, 32).
    * SDPX9B   - semidual port    - (bitwidth: 9, 18, 36).
    * DPB      - dual port        - (bitwidth: 16).
    * DPX9B    - dual port        - (bitwidth: 18).
    * SP       - single port      - (bitwidth: 1, 2, 4, 8, 16, 32).
    * SPX9     - single port      - (bitwidth: 9, 18, 36).

    For GW1NSR-4C and GW1NR-9 chips, SP/SPX9 primitives with data widths
    of 32/36 bits are implemented using a pair of 16-bit wide
    primitives.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-11-26 13:08:09 +01:00