caiyu/nextpnr
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4,799 Commits 22 Branches 7 Tags 17 MiB
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18 Commits

Author SHA1 Message Date
Miodrag Milanovic
6a6f7f56eb bump database version to 5 2024-11-21 14:53:43 +01:00
Miodrag Milanovic
ffb071167b removed not needed brackets 2024-11-21 14:52:43 +01:00
Miodrag Milanovic
5c46ab5f7e less horrid way of handling gfx ids 2024-11-21 14:52:43 +01:00
Miodrag Milanovic
49f098ad51 changed API and added tile wire id in db 2024-11-21 14:52:43 +01:00
gatecat
7c459805f6 himbaechel: Bump DB version for package extra_data addition 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-10-09 15:21:10 +02:00
Pepijn de Vos
028be1462a
apicula: add support for magic sip pins (#1370) 
* apicula: add support for magic sip pins

* fix nullptr check

* DDR fix by xiwang

* WIP support for setting the iostd

* add iostd
 2024-10-09 15:16:36 +02:00
Lofty
ccdc2f6f13 himbaechel/gowin: add timing information 2024-08-21 10:58:55 +01:00
gatecat
6683fd4ada himbaechel: Fix when more then 32k unique node shapes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-22 17:11:27 +01:00
gatecat
5bfe0dd1b1 himbaechel: Adding a xilinx uarch for xc7 with prjxray 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-14 17:12:09 +01:00
gatecat
cf647463e4 himbaechel: Add support for new constants API 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-07 09:00:03 +01:00
gatecat
d40c6e850d himbaechel: Generation speedup and improvements 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-10-29 07:46:45 +01:00
gatecat
3cac90a30a himbaechel: Fix for Python 3.9 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-09-13 14:35:58 +02:00
gatecat
3e1e783873 himbaechel: Initial timing support 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-09-08 09:55:49 +02:00
YRabbit
df13104384 gowin: Himbaechel. Add extra chip data 
To implement unusual IOs that have a dynamically changing configuration
 it is convenient to store the switching method in the additional chip
 data.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-08-31 08:28:09 +02:00
YRabbit
49f8620ac9 gowin: Himbaechel. Implement PLLs 
- The global router is modified to work out the routing of PLL outputs and inputs;
- Added API function to change wire type after its creation - there was
  a need to unify all wires included in the node at the stage of node
  creation, when all wires have already been created.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-08-31 08:28:09 +02:00
YRabbit
6cac19c055 gowin: Himbaechel. Add constraint file processing. 
- minor fixes for pinout saving;
- CST parser taken from generic-based apicula;
- $nextpnr IOB detachment is copied here because it is necessary to copy
  attributes from deleted bels.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-08-31 08:28:09 +02:00
YRabbit
3d3039e25c gowin: Himbaechel. Add bundle data generation. 
The pin data is only being populated so far, but not used.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-08-31 08:28:09 +02:00
gatecat
57b923a603 himbächel: Initial implementation 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-05-13 08:26:41 +02:00