Commit Graph

56 Commits

Author SHA1 Message Date
Miodrag Milanovic
c04c961949 Import spine data 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
05a191a014 Added LPF support 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
ca3d32e5ac make source more inline with ecp5 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
62ace58204 add missing bind and lutperm 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
7f8518d938 Import lutperm data 2023-05-04 14:23:08 +02:00
Lofty
398b2ab569 bitstream emission update 2023-05-04 14:23:08 +02:00
Lofty
235a575267 port ecp5 split slice to machxo2 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
ad5f6fccaa Use RelSlice, make more in line with ecp5 arch 2023-03-20 09:53:35 +01:00
gatecat
4111cc25d6 clangformat
Signed-off-by: gatecat <gatecat@ds0.me>
2023-03-17 09:31:38 +01:00
Miodrag Milanovic
6eb5f2a77e Enable wires and add dummy wire type for now 2023-03-16 13:37:23 +01:00
Miodrag Milanovic
7ad9914e51 Extend chipdb with metadata 2023-03-16 13:37:23 +01:00
Miodrag Milanovic
4396a646a7 Add simple BEL graphics 2023-03-16 13:37:23 +01:00
gatecat
7845b66512 Add missing <set> includes
Signed-off-by: gatecat <gatecat@ds0.me>
2023-01-20 09:04:41 +01:00
gatecat
603b60da8d api: add explain_invalid option to isBelLocationValid
Signed-off-by: gatecat <gatecat@ds0.me>
2022-12-07 10:27:58 +01:00
gatecat
e260ac33ab refactor: ArcBounds -> BoundingBox
Signed-off-by: gatecat <gatecat@ds0.me>
2022-12-07 10:00:53 +01:00
gatecat
76683a1e3c refactor: Use constids instead of id("..")
Signed-off-by: gatecat <gatecat@ds0.me>
2022-02-16 17:09:54 +00:00
gatecat
ddb084e9a8 archapi: Use arbitrary rather than actual placement in predictDelay
This makes predictDelay be based on an arbitrary belpin pair rather
than a arc of a net based on cell placement. This way 'what-if'
decisions can be evaluated without actually changing placement;
potentially useful for parallel placement.

A new helper predictArcDelay behaves like the old predictDelay to
minimise the impact on existing passes; only arches need be updated.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-12-19 17:15:15 +00:00
William D. Jones
b1f25d4b33 machxo2: Set Pip and Wire delays to reasonable fake values mirroring
estimateDelay.
2021-07-01 09:36:00 -04:00
gatecat
2ffb081442 Fixing old emails and names in copyrights
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-12 13:22:38 +01:00
gatecat
ecc19c2c08 Using hashlib in arches
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 15:05:19 +01:00
Keith Rothman
fe4608386e Split nextpnr.h to allow for linear inclusion.
"nextpnr.h" is no longer the god header.  Important improvements:

 - Functions in log.h can be used without including
   BaseCtx/Arch/Context. This means that log_X functions can be called
   without included "nextpnr.h"

 - NPNR_ASSERT can be used without including "nextpnr.h" by including
   "nextpnr_assertions.h".  This allows NPNR_ASSERT to be used safely in
   any header file.

 - Types defined in "archdefs.h" are now available without including
   BaseCtx/Arch/Context.  This means that utility classes that will be
   used inside of BaseCtx/Arch/Context can be defined safely in a
   self-contained header.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-15 09:05:23 -07:00
gatecat
7922b3bfc4 Replace DelayInfo with DelayPair/DelayQuad
This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.

This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.

While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-19 11:31:33 +00:00
gatecat
c7c13cd95f Remove isValidBelForCell
This Arch API dates from when we were first working out how to
implement placement validity checking, and in practice is little used by
the core parts of placer1/HeAP and the Arch implementation involves a
lot of duplication with isBelLocationValid.

In the short term; placement validity checking is better served by the
combination of checkBelAvail and isValidBelForCellType before placement;
followed by isBelLocationValid after placement (potentially after
moving/swapping multiple cells).

Longer term, removing this API makes things a bit cleaner for a new
validity checking API.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-16 13:31:36 +00:00
gatecat
33eca9a3d2 machxo2: Python bindings and stub GUI
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-12 10:40:03 +00:00
gatecat
8f5133d811 machxo2: Use snake_case for non-ArchAPI functions
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-12 10:36:59 +00:00
gatecat
b539363cd0 machxo2: Use IdStringLists in earnest
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-12 10:36:59 +00:00
gatecat
3f7618283d machxo2: Update with Arch API changes
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-12 10:36:59 +00:00
William D. Jones
0250aaaddd machxo2: clang format. 2021-02-12 10:36:59 +00:00
William D. Jones
5415194b39 machxo2: Checkpoint commit for slice bitstream generation. 2021-02-12 10:36:59 +00:00
William D. Jones
cf2db7a4c4 machxo2: Write out pips to bitstream. 2021-02-12 10:36:59 +00:00
William D. Jones
695fb7e569 machxo2: Add/fix copyright banners. 2021-02-12 10:36:59 +00:00
William D. Jones
e1f72318e0 machxo2: Tweak A-star parameters for acceptable performance. 2021-02-12 10:36:59 +00:00
William D. Jones
447b3a060c machxo2: Fix getWireName. 2021-02-12 10:36:59 +00:00
William D. Jones
385917059b machxo2: Fix typos where absolute positions were treated as relative. 2021-02-12 10:36:59 +00:00
William D. Jones
722d1f2542 machxo2: Finish implementing Wire API functions. nextpnr segfaults on example with constraints. 2021-02-12 10:36:59 +00:00
William D. Jones
861c12e6eb machxo2: Finish implementing Pip API functions. 2021-02-12 10:36:59 +00:00
William D. Jones
0adde4aede machxo2: Implement 4 more Wire/Pip API functions. 2021-02-12 10:36:59 +00:00
William D. Jones
19a9554bda machxo2: Add stub getAttrs API functions. 2021-02-12 10:36:59 +00:00
William D. Jones
9a9054188c machxo2: Implement getByName/getName for Wires and Pips. 2021-02-12 10:36:59 +00:00
William D. Jones
9c37aef499 machxo2: Detect LOC attributes during packing to implement rudimentary user constraints. 2021-02-12 10:36:59 +00:00
William D. Jones
0e63178fe1 machxo2: clang format. 2021-02-12 10:36:59 +00:00
William D. Jones
91ad064249 machxo2: Import remaining iterators from ECP5. 2021-02-12 10:36:59 +00:00
William D. Jones
a7917c9c63 machxo2: Implement WireId/PipId, complete Bel part of API. 2021-02-12 10:36:59 +00:00
William D. Jones
bbc683dd75 machxo2: Implement all of Bel API except getBelPinWire. 2021-02-12 10:36:59 +00:00
William D. Jones
5f748272fc machxo2: Implement bel_to_cell and API functions using it. 2021-02-12 10:36:59 +00:00
William D. Jones
682de724a8 machxo2: Implement 2 Bel API functions. 2021-02-12 10:36:59 +00:00
William D. Jones
3e6be4bbfd machxo2: Implement General Methods. 2021-02-12 10:36:59 +00:00
William D. Jones
094233a4ab machxo2: Implement getBelLocation to stop std::out_of_range in place phase. 2021-02-12 10:36:59 +00:00
William D. Jones
52b424c385 machxo2: Convert uint_t to int_t in packed structs. 2021-02-12 10:36:59 +00:00
William D. Jones
dc07054ee8 machxo2: Implement functions to get device utilization (throws std::out_of_range during place phase). 2021-02-12 10:36:59 +00:00