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Author SHA1 Message Date
gatecat
ff48ad83be interchange: Bump versions 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-21 10:00:35 +01:00
gatecat
bae83857a3 interchange: Add macro parameter mapping 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-21 10:00:35 +01:00
gatecat
64f5b1d031 interchange: Don't error out on missing cell ports 
This is required for LUTRAM support, as the upper address bits of
RAMD64E etc are missing for shallower primitives.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-21 10:00:35 +01:00
gatecat
a146dbdb03 interchange: Add LUTRAM test 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-21 10:00:35 +01:00
gatecat
2759480cb5 interchange: Preliminary implementation of macro expansion 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-21 10:00:35 +01:00
gatecat
237b27e50b interchange: Add macro param map rules to chipdb 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-21 10:00:35 +01:00
gatecat
012b60c9ca interchange: Add macro data to chipdb 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-21 10:00:35 +01:00
gatecat
81818fd38c
Merge pull request #712 from YosysHQ/gatecat/rr-heatmap 
router2: Add heatmap by routing resource type
 2021-05-21 09:59:19 +01:00
gatecat
54b8364cea
Merge pull request #711 from acomodi/interchange-site-to-pseudo-pips 
interchange: phys: add site instance idstr for pseudo tile PIPs
 2021-05-20 19:45:27 +01:00
Alessandro Comodi
9dce00a4e7 gh-actions: interchange: use commit sha as cache key 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-05-20 19:57:03 +02:00
Alessandro Comodi
6e22a9ea97 bump interchange schema 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-05-20 19:24:53 +02:00
gatecat
1595c07260 router2: Add heatmap by routing resource type 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-20 14:54:23 +01:00
Alessandro Comodi
84359f39c5 interchange: phys: add site instance idstr for pseudo tile PIPs 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-05-19 18:48:54 +02:00
gatecat
5a41d2070c Run clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-16 16:25:05 +01:00
gatecat
179ae683cc
Merge pull request #708 from Ravenslofty/mistral-getchipname 
mistral: add getChipName
 2021-05-15 22:59:46 +01:00
Lofty
b81ba2d6c2 mistral: add getChipName 
Signed-off-by: Lofty <dan.ravensloft@gmail.com>
 2021-05-15 22:50:56 +01:00
gatecat
47b4e42b1c
Merge pull request #707 from gatecat/cyclonev 
mistral: Initial Cyclone V support
 2021-05-15 22:37:19 +01:00
gatecat
3eeb2b20eb Update README 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 21:51:56 +01:00
gatecat
9d7f90dd89 mistral: Add MISTRAL_CLKBUF cell type 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 21:28:48 +01:00
gatecat
6cef569155 ci: Use GH only for Mistral and fpga-interchange 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 15:53:25 +01:00
gatecat
3bb94192d5 mistral: Tidying up 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
b1e1492dac mistral: Make router2 the default 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
f318898474 router2: Hacky workaround for slow Cyclone V convergence 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
7fbfd98b8a mistral: Speed up bel binding and checking 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
34677d3883 mistral: Workaround for weird SCLR issue 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
9221acc9e2 mistral: Fix ENA and ACLR bitstream generation 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
4d32c4f2fc mistral: Disable global buffers that are currently broken 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
511e46c40f router2: Reduce verbosity when debugging 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
e1aaf715c6 mistral: Compensate for EF_SEL mirroring in validity check 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
87ebada258 mistral: Fix EF_SEL and BTO_DIS 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
8bc9732d49 mistral: PKREG bits appear to be mirrored within a half? 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
757a10c247 mistral: Debugging flipflops 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
dce847b2f3 mistral: Trim SDATA if SLOAD is low 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
b29fa1d24c mistral: FF&CLKBUF fixes, part 1 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
66b3a192f8 mistral: First pass at FF and CLKBUF bitgen 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
b2f45b1aab mistral: Account for TD input count limit 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
bd525d3548 msitral: Fix pip iterator Python bindings 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
8c7fa8e6c9 mistral: Implement PIP locations, too 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
6ad329c540 mistral: Implement bounding boxes for router2 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
e688ee0e89 mistral: Debugging carry chain issues 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
3313d5267a mistral: Adding FF control set reservation 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
09a867310b mistral: Carry fixes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
3d1bb4f1b2 mistral: Carry debugging 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
2f2fde7e6c mistral: Write arith mode to bitstream (not yet functional) 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
d39e67da7e mistral: First pass at carry packing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
7574eab2b6 mistral: FF validity checking fixes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
18e05ec852 mistral: Fix constant trimming 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
bacba274a2 mistral: Write LUT inits 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
d1f635242d mistral: Add some IO configuration 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat
dea4c6f53f mistral: Setting some more boilerplate bits 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00