Commit Graph

3003 Commits

Author SHA1 Message Date
gatecat
1b6cdce925
Merge pull request #575 from YosysHQ/gatecat/belpin-2
Support for cell pin to bel pin mappings
2021-02-15 09:38:22 +00:00
gatecat
f1ccc0e205
Merge pull request #582 from litghost/add_xdc_parser
Add XDC parser to FPGA interchange
2021-02-12 22:40:41 +00:00
Keith Rothman
033cc6731b Add FPGA interchange tests to CI.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-12 13:48:50 -08:00
Keith Rothman
5312945757 Update tests to include XDC unit test.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-12 10:31:05 -08:00
Keith Rothman
82ab3c1aad Run "make clangformat".
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-12 10:31:05 -08:00
Keith Rothman
8a860857ea Remove capnp and libz for XDC parser PR.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-12 10:31:05 -08:00
Keith Rothman
c96d0f225c Refactor XDC parser into a little class for testing purposes.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-12 10:31:04 -08:00
Keith Rothman
d987bd2997 Add unknown handles to convert [0] to "[0]".
Tcl reads something like "set port [get_ports x[0]]" as "invoke proc 0
with zero arguments", rather than just "[0]".  To prevent exposing
non-Tcl users this, "[<number>]" just return themselves.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-12 10:31:04 -08:00
Keith Rothman
a0bd313139 Add FPGA interchange XDC parser.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-12 10:31:04 -08:00
gatecat
cede682585
Merge pull request #579 from litghost/add_control_for_split_io
Add control to whether GenericFrontend splits IO ports.
2021-02-12 18:22:06 +00:00
Keith Rothman
e28dedbbe3 Update docs.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-12 08:07:09 -08:00
gatecat
c956cae824 Make BaseArch getDecalGraphics return an empty range
Fix assertion failure when opening the GUI on an arch without any
decals.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-12 10:35:51 +00:00
gatecat
ad7bb51030
Merge pull request #580 from litghost/add_design_loaded_state_variable
Add design_loaded state variable.
2021-02-12 09:54:15 +00:00
gatecat
5dfbe703ae
Merge pull request #581 from litghost/add_isbelhidden
Add getBelHidden and add some missing "override" statements.
2021-02-12 09:53:50 +00:00
Keith Rothman
99e397000c Add getBelHidden and add some missing "override" statements.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-11 14:58:02 -08:00
Keith Rothman
96293ab25e Add design_loaded state variable.
This is to decouple the command line flag "--json" and enable other
frontend's.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-11 13:43:23 -08:00
Keith Rothman
73710416b4 Add control to whether GenericFrontend splits IO ports.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-11 13:33:55 -08:00
gatecat
7c7d69e1d2 router2: Support for multiple bel pins per cell pin
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-10 15:14:44 +00:00
gatecat
7dafc64f78 router1: Support for multiple bel pins per cell pin
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-10 14:46:03 +00:00
gatecat
535723f414 Start making use of getBelPinsForCellPin API
This replaces getNetinfoSinkWire with 3 new functions for different use
cases.

At the moment all existing code has been moved to getNetinfoSinkWire
with phys_idx=0 so the build doesn't break; but this won't yet function
properly with more than one sink. But it provides a base on which to
work on refactoring the routers to support this case.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-10 14:18:12 +00:00
gatecat
85bb108ba4 Add getBelPinsForCellPin to Arch API
This is a basic implementation, without considering "M of N"
arrangements (e.g. for LUT permuation where you only want to route to 1
out of 4/6 sinks) or using a type other than IdString to identify bel
pins.

But this is also enough to start working out where in nextpnr will break
due to removing the 1:1 cell:bel pin cardinality, as a next step.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-10 11:54:54 +00:00
gatecat
e376f950fe
Merge pull request #574 from YosysHQ/gatecat/belpin-1
Remove the unused CellInfo::pins field
2021-02-10 11:27:11 +00:00
gatecat
6bd3dba1e3 Remove the unused CellInfo::pins field
No arches ever actually used this to implement a Cell->Bel pin mapping,
and in practice if any did try they would inevitably hit bitrot.

This field had limited use in practice as it is necessary to also
support cases where one cell pin maps to more than one bel pin. Removing
this old field is the first step towards developing a new API for this.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-10 10:42:26 +00:00
gatecat
f67d474edc
Merge pull request #573 from YosysHQ/gatecat/basearchranges
Add BaseArchRanges for default ArchRanges types
2021-02-09 11:30:23 +00:00
gatecat
11db5a2f1d Add BaseArchRanges for default ArchRanges types
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-09 10:39:14 +00:00
gatecat
1febb80a1e Add nextpnr-gowin binary to gitignore
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-09 10:36:03 +00:00
gatecat
bcf81f0e71
Merge pull request #568 from YosysHQ/dave/arch-override
Create a new BaseArch that formally specifies the Arch API and provides some base implementations
2021-02-08 17:56:08 +00:00
gatecat
2932dc3985 Make BaseCtx destructor virtual
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-08 17:03:22 +00:00
D. Shah
f501ba0c77 Update prjoxide URL
Signed-off-by: D. Shah <gatecat@ds0.me>
2021-02-08 13:04:49 +00:00
David Shah
23edefa0b5
Merge pull request #572 from YosysHQ/dave/more-ssize
Use RelSlice::ssize instead of cast-to-int throughout
2021-02-08 12:05:58 +00:00
D. Shah
0d444bfc6e Use RelSlice::ssize instead of cast-to-int throughout
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-08 11:24:00 +00:00
D. Shah
697c4fd08b Update docs with API changes
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-08 11:08:45 +00:00
D. Shah
9deb9e6e85 interchange: Base on ArchAPI
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-08 10:41:03 +00:00
D. Shah
efca63862c Use 'T' postfix to disambiguate LHS and RHS of using
Arches might otherwise have range types named ambigiously with the entry
in ArchRanges.

Signed-off-by: D. Shah <dave@ds0.me>
2021-02-08 10:29:50 +00:00
D. Shah
3e631fe2f4 Add archArgs and archArgsToId to Arch API
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-05 19:19:17 +00:00
D. Shah
6575bfac3e gowin: Switch to BaseArch
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-05 19:19:17 +00:00
D. Shah
c7ef7e1902 generic: Base upon ArchAPI
As generic is often picked as our 'odd-one-out' we also use it as an
example of an Arch that does not build upon BaseArch.

Signed-off-by: D. Shah <dave@ds0.me>
2021-02-05 19:19:17 +00:00
D. Shah
f5d2e245e1 nexus: Switch to BaseArch
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-05 19:19:17 +00:00
D. Shah
59c3db46ca ice40: Switch to BaseArch
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-05 19:19:17 +00:00
D. Shah
a8a27299ae Add pure-virtual ArchAPI interface
This splits out the pure-virtual definition of the architecture API into
ArchAPI; leaving BaseArch to only provide default implementations (which
can now be completely opted out of by deriving from ArchAPI instead of
BaseArch).

Signed-off-by: D. Shah <dave@ds0.me>
2021-02-05 19:19:17 +00:00
D. Shah
b4227f586c Rename ArchBase to BaseArch for consistency with BaseCtx
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-05 19:19:17 +00:00
D. Shah
297cd026b9 Add default implementation of bel bucket functions
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-05 19:19:17 +00:00
D. Shah
ed8e3c83d9 Add default implementation of some range-returning functions
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-05 19:19:17 +00:00
D. Shah
6d794abf49 Add a few more functions to ArchBase
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-05 19:19:17 +00:00
D. Shah
d4363b7ee5 ecp5: Use common wire/pip binding
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-05 19:19:17 +00:00
D. Shah
b866601b63 Fix now-illegal use of reinterpret_cast
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-05 19:19:17 +00:00
D. Shah
ba5568d501 nextpnr: Example of shared wire/bel/pip binding code
Currently not actually being tested

Signed-off-by: D. Shah <dave@ds0.me>
2021-02-05 19:19:17 +00:00
D. Shah
cfa9a9daec nextpnr: Use templates to specify range types
Signed-off-by: D. Shah <dave@ds0.me>
2021-02-05 19:19:17 +00:00
D. Shah
8f76af40db nextpnr: Add base virtual functions for non-range Arch API
This makes the Arch API clearer and also allows a base implementation of
functions to reduce the amount of complexity to get a basic Arch up and
running.

Currently this only implements these for functions that don't return a
range. Range-returning functions will require more work in order due to
the current 'duck typing' approach (probably a struct that contains the
range types combined with templating.)

Signed-off-by: D. Shah <dave@ds0.me>
2021-02-05 19:19:17 +00:00
David Shah
8b4163b77c
Merge pull request #567 from litghost/initial_fpga_interchange
Initial FPGA interchange arch
2021-02-05 19:15:29 +00:00