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Author SHA1 Message Date
Miodrag Milanovic
901ad4e917 Update git ignore locations 2020-06-27 13:18:06 +02:00
David Shah
9eb6e549c5 Update some URLs 
Signed-off-by: David Shah <dave@ds0.me>
 2020-06-26 11:43:27 +01:00
David Shah
4f4aa53120
Merge pull request #460 from whitequark/better-embed 
Simplify and improve chipdb embedding/loading
 2020-06-26 11:32:13 +01:00
whitequark
89e0cc8078 Simplify and improve chipdb embedding/loading. 2020-06-26 08:36:07 +00:00
David Shah
2873133479 Update COPYING 
Signed-off-by: David Shah <dave@ds0.me>
 2020-06-25 19:45:18 +01:00
David Shah
1df8ac805a HeAP: Add timeout to IO placement 
Signed-off-by: David Shah <dave@ds0.me>
 2020-06-25 19:42:53 +01:00
whitequark
19a3095ecb Fix typo 2020-06-25 17:26:57 +00:00
David Shah
dc209f6344
Merge pull request #459 from whitequark/better-chipdb 
CMake: rewrite chipdb handling from ground up
 2020-06-25 15:39:54 +01:00
whitequark
bf8d4c428e CMake: require at least version 3.5 (Ubuntu 16.04). 2020-06-25 14:03:37 +00:00
whitequark
1dc1164dce CMake: rewrite chipdb handling from ground up. 2020-06-25 14:03:37 +00:00
whitequark
23d19a254d CMake: only request a CXX compiler. 2020-06-24 13:22:49 +00:00
David Shah
7decb6526b
Merge pull request #458 from whitequark/patch-1 
Remove dead links from README
 2020-06-24 08:27:32 +01:00
whitequark
1f061b5a97
Remove dead links from README 2020-06-24 07:24:29 +00:00
David Shah
93dbb53371
Merge pull request #457 from whitequark/better-bba 
CMake: promote bba to a true subproject
 2020-06-24 07:09:08 +01:00
whitequark
4c7aedcf4e CMake: promote bba to a true subproject. 2020-06-23 10:47:18 +00:00
David Shah
c9e7d1448e clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2020-06-12 16:19:14 +01:00
David Shah
3c078f6090
Merge pull request #454 from YosysHQ/ecp5-global-place 
ecp5: Fix placement of DCCs to guarantee routeability
 2020-06-10 18:12:06 +01:00
David Shah
43fd9e6779 ecp5: Fix placement of DCCs to guarantee routeability 
Signed-off-by: David Shah <dave@ds0.me>
 2020-06-10 15:47:47 +01:00
David Shah
be50947fa6
Merge pull request #452 from smunaut/ice40_shiftreg_div_mode 
ice40: Add support for the 2nd bit of SHIFTREG_DIV_MODE
 2020-06-02 19:55:31 +01:00
Sylvain Munaut
9b71bba747 ice40: Add fallback behavior for Extra Cell config bits vectors 
This helps make new nextpnr compatible with old chipdbs when a parameters
goes from single bit to multi bit.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2020-06-02 20:21:16 +02:00
Sylvain Munaut
5e2b6bcef9 ice40: Add support for the 2nd bit of SHIFTREG_DIV_MODE 
This requires the matching chipdb update from icestorm project !

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2020-06-02 11:03:04 +02:00
David Shah
f44498a530
Merge pull request #447 from whitequark/wasi 
Port nextpnr-{ice40,ecp5} to WASI
 2020-05-24 14:23:35 +01:00
whitequark
e7bb04769d Port nextpnr-{ice40,ecp5} to WASI. 
This involves very few changes, all typical to WASM ports:
  * WASM doesn't currently support threads or atomics so those are
    disabled.
  * WASM doesn't currently support exceptions so the exception
    machinery is stubbed out.
  * WASM doesn't (and can't) have mmap(), so an emulation library is
    used. That library currently doesn't support MAP_SHARED flags,
    so MAP_PRIVATE is used instead.

There is also an update to bring ECP5 bbasm CMake rules to parity
with iCE40 ones, since although it is possible to embed chipdb into
nextpnr on WASM, a 200 MB WASM file has very few practical uses.

The README is not updated and there is no included toolchain file
because at the moment it's not possible to build nextpnr with
upstream boost and wasi-libc. Boost requires a patch (merged, will
be available in boost 1.74.0), wasi-libc requires a few unmerged
patches.
 2020-05-23 20:57:26 +00:00
David Shah
2d406f3e27
Merge pull request #440 from YosysHQ/lattice-fixes 
Fixes for the Lattice SERDES eye demo designs
 2020-05-18 09:38:41 +01:00
David Shah
ddf546c2cc clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2020-05-16 12:57:24 +01:00
David Shah
0fb7746c20
Merge pull request #442 from nategraff-sifive/fix-unsupported-spelling 
Fix spelling of 'unsupported'
 2020-05-14 22:10:06 +01:00
Miodrag Milanović
f8cf206826
Merge pull request #441 from YosysHQ/eddie/fix_topo 
Fix embarassing use of topographical when meaning topological
 2020-05-14 19:08:22 +02:00
Miodrag Milanović
34bc421626
Merge pull request #439 from edbordin/master 
Minor patch for MinGW build
 2020-05-14 19:07:49 +02:00
Eddie Hung
e6b85f1bc0 Fix embarassing use of topographical when meaning topological 2020-05-14 08:55:28 -07:00
David Shah
163dee1e1a ecp5: Disconnect dedicated DCU inputs if connected to constants 
Signed-off-by: David Shah <dave@ds0.me>
 2020-05-14 13:26:56 +01:00
David Shah
3c60ea383d ecp5: Improve global routing robustness 
Signed-off-by: David Shah <dave@ds0.me>
 2020-05-14 13:12:30 +01:00
David Shah
2aaef61547 ecp5: Don't promote VCC/GND to globals even if connected to clock port 
Signed-off-by: David Shah <dave@ds0.me>
 2020-05-14 13:07:59 +01:00
David Shah
2cebd40f2e lpf: Support // comments 
Signed-off-by: David Shah <dave@ds0.me>
 2020-05-14 13:06:58 +01:00
Ed Bordin
7b84ed94b5 minor patch for MinGW build 2020-05-14 16:35:55 +10:00
Nathaniel Graff
08f68518f2 Fix spelling of 'unsupported' 
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
 2020-05-13 20:00:37 -07:00
David Shah
2692c6f6cc
Merge pull request #437 from miek/lvcmos33d-drive 
ecp5: Allow setting drive strength for LVCMOS33D IOs
 2020-05-12 14:24:18 +01:00
Mike Walters
5b660e3432 ecp5: Allow setting drive strength for LVCMOS33D IOs 2020-05-12 14:19:37 +01:00
David Shah
e431d1a33f Add missing --top option 
Signed-off-by: David Shah <dave@ds0.me>
 2020-05-09 19:47:03 +01:00
David Shah
0faf07aac8 Merge branch 'rschlaikjer-rschlaikjer-mult18x18-register-timings' 2020-05-01 08:17:52 +01:00
David Shah
84327b634c ecp5: MULT18X18D timing fixes 
Signed-off-by: David Shah <dave@ds0.me>
 2020-05-01 08:17:29 +01:00
Ross Schlaikjer
a1160068c8
No cell delay for clocked MULT18X18D 2020-04-30 11:09:22 -04:00
Ross Schlaikjer
de6ddc470b
Further condense 2020-04-29 14:52:29 -04:00
Ross Schlaikjer
6e8082860e
Dedupe clock error check 2020-04-29 14:46:09 -04:00
Ross Schlaikjer
0043ae0807
Issue warning for mixed-mode inputs 2020-04-29 14:39:52 -04:00
Ross Schlaikjer
6625284950
Handle register timing case 2020-04-29 13:58:52 -04:00
Ross Schlaikjer
a4fa953740
Use registered port class on mult18x18 2020-04-29 11:08:53 -04:00
Ross Schlaikjer
5e763b1afc
Alter MULT18X18D timing db based on register config 
If the REG_INPUTA_CLK and REG_INPUTB_CLK values are set, then we should
use the faster setup/hold timings for the 18x8 multiplier.
Similarly, check the value of REG_OUTPUT_CLK for whether or not to use
faster timings for the output.

This is based on how I currently understand the registers to work - if
anyone knows the actual rules for when each timing applies please do
chime in to correct this implementation if necessary.

Along the same lines, this PR does not address the case when the
pipeline registers are enabled, since it is not clear to me how exactly
that affects the timing.
 2020-04-28 20:01:29 -04:00
David Shah
5c6b2cbafe
Merge pull request #433 from YosysHQ/dave/pyfixes 
python: Miscellaneous fixes
 2020-04-24 19:01:04 +01:00
David Shah
25938500d6 python: Also convert regular map keys to string 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-24 18:23:03 +01:00
David Shah
8f1683246e python: Improve general robustness during autocomplete 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-24 16:44:30 +01:00