Olivier Galibert
206bb07506
mistral: Add support for cyclonev_hps_interface_mpu_general_purpose
2021-10-14 17:04:32 +02:00
gatecat
4e1f2d7deb
Merge pull request #845 from YosysHQ/gatecat/mlab-cluster-fix
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mistral: Fix MLAB clustering
2021-10-11 21:07:41 +01:00
gatecat
15c10796bd
mistral: Fix MLAB clustering
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-10-11 20:12:56 +01:00
gatecat
dd2c5942a4
clangformat
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-10-11 19:35:23 +01:00
gatecat
349cbdf9da
Merge pull request #843 from Ravenslofty/lofty/mistral-basic-timing
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mistral: very basic timing info
2021-10-11 14:35:28 +01:00
Lofty
0a0c9393c1
mistral: very basic timing info
2021-10-10 23:56:58 +01:00
gatecat
9963f76583
Merge pull request #844 from pepijndevos/patch-2
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Gowin: more clearly mark dummy pips
2021-10-10 20:27:21 +01:00
Pepijn de Vos
603f44e947
Gowin: more clearly mark dummy pips
2021-10-10 18:11:02 +02:00
gatecat
e546cd00de
Merge pull request #842 from yrabbit/delays
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gowin: Replace the zero delays with reasonable values.
2021-10-09 21:52:18 +01:00
gatecat
8ad74edd66
router2: Disable criticality sorting towards end of routing
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-10-09 20:56:45 +01:00
YRabbit
95217e7dd2
Merge branch 'master' into delays
2021-10-09 20:33:48 +10:00
YRabbit
bfe9cd548a
gowin: Replace the zero delays with reasonable values.
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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2021-10-09 20:26:18 +10:00
gatecat
520aec3ef4
Merge pull request #841 from Ravenslofty/lofty/mistral-cleanup
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mistral: clean up bel init slightly
2021-10-08 18:00:13 +01:00
Lofty
4c8a8003d3
mistral: clean up bel init slightly
2021-10-08 15:21:21 +01:00
gatecat
b749ef5f56
hashlib: Support for std::array keys
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-10-07 17:05:16 +01:00
gatecat
74e7beb5e1
Merge pull request #839 from yrabbit/wide-luts
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gowin: add support for wide LUTs.
2021-10-07 13:08:01 +01:00
YRabbit
c72ea15472
gowin: add support for wide LUTs.
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* A hardwired MUX within each logical cell is used.
* The delay is equal 0.
* No user placement constraints.
* The output route contains dummy PIPs. They are ignored by gowin_pack, but it may be worth removing them.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2021-10-07 18:38:33 +10:00
gatecat
4f17a1711a
Merge pull request #837 from YosysHQ/gatecat/mistral-mlab-2
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mistral: Adding support for MLABs as memory
2021-10-05 13:59:36 +01:00
gatecat
f5f7ef6864
mistral: Adding support for MLABs as memory
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-10-05 12:40:47 +01:00
gatecat
9c32e2d852
Merge pull request #836 from YosysHQ/gatecat/mistral-mlab
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mistral: Add bel pins for MLAB write port
2021-10-03 18:49:42 +01:00
gatecat
fe31fba623
mistral: Add bel pins for MLAB write port
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-10-03 15:18:41 +01:00
gatecat
4d97e29999
Merge pull request #834 from YosysHQ/gatecat/cygwin
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Fix Cygwin build
2021-10-01 17:11:59 +01:00
gatecat
211b6b6b06
Fix Cygwin build
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-10-01 12:40:56 +01:00
gatecat
5ae9eeba18
Merge pull request #833 from antmicro/interchange-fix-uninitialized-memory-bug
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interchange: fix uninitialized memory bug in cluster placement
2021-10-01 12:38:05 +01:00
Alessandro Comodi
a3ba83fce3
interchange: fix uninitialized memory bug in cluster placement
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-10-01 11:53:56 +02:00
gatecat
7550b60069
Merge pull request #828 from YosysHQ/gatecat/interchange-warn-fix
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interchange: Enable Werror on CI and fix some compile warnings
2021-09-30 11:05:32 +01:00
gatecat
bd137a8b50
Merge pull request #810 from antmicro/write-timing-report
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Timing report in JSON format
2021-09-29 15:10:28 +01:00
Maciej Kurc
1db3a87c62
Code formatting
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-09-29 14:59:09 +02:00
Maciej Kurc
76f5874ffc
Brought back printout of critical path source file references, added clk-to-q, source and setup segment types
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-09-29 10:16:45 +02:00
gatecat
8b3e6711bc
Merge pull request #830 from yrabbit/mistype
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Fix mistype.
2021-09-29 06:40:30 +01:00
YRabbit
ddc368f0dd
Fix mistype.
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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2021-09-29 14:21:06 +10:00
Maciej Kurc
1ed692aca9
Shifted moving of data containers after printing
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-09-28 18:01:30 +02:00
Maciej Kurc
9018782eaa
Added a commandline option controlled writeout of per-net timing details
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-09-28 17:42:51 +02:00
Maciej Kurc
a9df3b425f
Added description of the JSON report structure.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-09-28 17:42:51 +02:00
Maciej Kurc
6deff56e83
Moved timing result report storage to the context, added its writeout to the current utilization and fmax report
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-09-28 17:42:51 +02:00
Maciej Kurc
c6dc1f535a
Added reporting critical paths in JSON format
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-09-28 17:42:51 +02:00
Maciej Kurc
d8571b6c00
Decoupled critical path report generation from its printing
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-09-28 17:42:51 +02:00
Maciej Kurc
12adbb81b1
Switched to JSON format for timing analysis report
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-09-28 17:42:51 +02:00
Maciej Kurc
99ae5ef38e
Added writing a CSV report with timing analysis of each net branch
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-09-28 17:42:51 +02:00
gatecat
19afb07370
interchange: Fix compile warnings
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-09-28 10:11:09 +01:00
gatecat
d89afc2aa6
ci: Enable -Werror for interchange arch
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-09-28 09:42:25 +01:00
gatecat
9d8d3bdbc4
Merge pull request #827 from YosysHQ/gatecat/idstring-in
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idstring: Add 'in' function from Yosys
2021-09-27 22:03:11 +01:00
gatecat
0b0baf3446
idstring: Add 'in' function
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-09-27 19:18:40 +01:00
gatecat
535b2490c4
Merge pull request #812 from antmicro/MacroCells
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Convert macros to clusters for better placement
2021-09-27 17:50:55 +01:00
Maciej Dudek
ea489f6d93
Fix small isses and code formatting
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Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
2021-09-27 16:16:33 +02:00
gatecat
9782a46a9b
ci: Bump prjoxide version
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-09-24 19:21:44 +01:00
gatecat
d44b6acaa9
Merge pull request #826 from YosysHQ/gatecat/nexus-lutperm
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nexus: Add LUT permutation support
2021-09-24 19:20:36 +01:00
gatecat
718ee441a0
nexus: Add resource cost overrides
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-09-24 19:19:26 +01:00
gatecat
ab6990f908
router2: Allow overriding resource costs
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-09-24 19:11:37 +01:00
gatecat
502fcff765
nexus: LUT permutation support
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-09-24 15:26:16 +01:00