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Author SHA1 Message Date
YRabbit
d6fdd6c7ce Merge branch 'combine-dff' into extend-placement 2021-09-04 17:39:09 +10:00
YRabbit
e4701f2da1 Merge branch 'master' into extend-placement 2021-09-04 16:29:21 +10:00
gatecat
fd6366f027 nexus: Fix getBelGlobalBuf 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-02 17:23:11 +01:00
gatecat
01b51fb715 router2: Fix explored count 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-02 17:08:54 +01:00
YRabbit
e82d49e13a Merge branch 'master' into combine-dff 2021-09-02 18:19:30 +10:00
gatecat
0c40bed425
Merge pull request #790 from acomodi/place-only-same-cluster-in-site 
interchange: place only cells belonging to the same clusters in the same site
 2021-08-31 12:37:04 +01:00
Alessandro Comodi
e0950408d5 interchange: clusters: fix other cluster allowance checks in same site 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-08-31 12:44:36 +02:00
Alessandro Comodi
2df931f7db interchange: entirely disable cache when binding site routing 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-08-31 12:08:46 +02:00
Alessandro Comodi
85cf6562b6 gh: interchange: bump python-interchange tag 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-08-31 11:54:22 +02:00
YRabbit
f3899696a7 gowin: Place DFFs of different types in the slice. 
Allow the registers of the same type or pairs shown below to be
placed in the same slide:

|--------|--------|
| DFFS   | DFFR   |
| DFFSE  | DFFRE  |
| DFFP   | DFFC   |
| DFFPE  | DFFCE  |
| DFFNS  | DFFNR  |
| DFFNSE | DFFNRE |
| DFFNP  | DFFNC  |
| DFFNPE | DFFNCE |

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2021-08-31 07:53:15 +10:00
YRabbit
23a5e91858 gowin: Add constraints on primitive placement. 
Added support for the INS_LOC instruction in the constraints file
(.CST), which is used to specify object placement.
Expanded treatment of IO_LOC/IO_PORT constraints, which now can
be applied to both ports and IO buffers.
Port constraints have priority.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2021-08-31 07:36:11 +10:00
Alessandro Comodi
78bf5796db interchange: disallow placing cells on sites with clusters 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-08-27 13:47:10 +02:00
gatecat
0e83db47a0 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-26 14:58:43 +01:00
gatecat
7f8e467acd
Merge pull request #805 from YosysHQ/gatecat/py-portref-byvalue 
python: Wrap PortRef by value
 2021-08-26 14:57:46 +01:00
gatecat
b85fe12234 python: Wrap PortRef by value 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-26 13:23:16 +01:00
gatecat
6fc41692d6
Merge pull request #710 from Ravenslofty/mistral-mlab-as-lab 
mistral: Use MLABs as if they're LABs (for now)
 2021-08-24 18:25:44 +01:00
gatecat
0367719eea mistral: Permute MLAB init bits correctly 2021-08-24 15:39:45 +01:00
gatecat
e15f0db408 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-24 12:48:08 +01:00
gatecat
86393c8c8e
Merge pull request #801 from yrabbit/TRBL-style 
gowin: Add the IO[TRBL]style placement recognition
 2021-08-23 21:58:08 +01:00
gatecat
42166f2e3e
Merge pull request #802 from YosysHQ/gatecat/python-rt-dly 
python: Allow querying route delays
 2021-08-23 21:56:42 +01:00
gatecat
de311e052f python: Allow querying route delays 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-23 20:51:53 +01:00
YRabbit
e4196f32d3 gowin: Add the IO[TRBL]style placement recognition 
Specifying pin placement with this notation (e.g. IOR4B) allows
to use the same constraint file without changes for different
packages and even different families.
The vendor router also understands this notation.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2021-08-23 16:19:02 +10:00
gatecat
897a2fccb6
Merge pull request #798 from kleinai/extref-loc 
Make EXTREFB handling more robust
 2021-08-19 16:36:18 +01:00
gatecat
6ae9b47155
Merge pull request #800 from smunaut/fix_py_portrefvector 
pybindings: Fix mapping for PortRefVector
 2021-08-19 12:36:32 +01:00
Sylvain Munaut
df67783dd3 pybindings: Fix mapping for PortRefVector 
This is used by net.users for instance.

Removed by mistake in 4ac00af6fa

Fixes #799

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2021-08-19 12:01:49 +02:00
Aidan Klein
e6006805ce Make EXTREFB handling more robust 
Avoids a segfault if an EXTREFB does not connect directly to its associated DCUA.
Also adds location constraints specifically for EXTREFB.
 2021-08-18 20:49:55 -04:00
Lofty
b88e86f366 mistral: Use MLABs as if they're LABs (for now) 
Signed-off-by: Lofty <dan.ravensloft@gmail.com>
 2021-08-17 16:02:49 +01:00
gatecat
b37d133c43
Merge pull request #794 from YosysHQ/gatecat/router2p5 
router2: Improved bidir routing and timing-driven ripup option
 2021-08-16 14:08:20 +01:00
gatecat
f207068ee2 router2: Add experimental timing-driven ripup option 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-15 16:22:03 +01:00
gatecat
42522c492c router2: Alternative congestion cost schedule 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-15 16:22:03 +01:00
gatecat
2a856db72c router2: Adding some criticality heuristics 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-15 16:22:03 +01:00
gatecat
64f6b8bc67 router2: Improved bidir routing and data structures 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-15 16:22:03 +01:00
gatecat
4d54b62e63
Merge pull request #795 from YosysHQ/gatecat/mistral-include-fix 
mistral: Include mistral generated files in include dirs
 2021-08-15 16:20:51 +01:00
gatecat
f7be385230 mistral: Include mistral generated files in include dirs 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-15 15:13:31 +01:00
gatecat
e7db15d6a4 mistral: Fix pip binding check 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-14 20:23:05 +01:00
gatecat
a66cd0200b clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-14 20:22:54 +01:00
gatecat
b0a4f1b86e
Merge pull request #793 from gregdavill/ecp5_diff_od 
ecp5: Enable OPENDRAIN on differential outputs
 2021-08-14 13:48:55 +01:00
Greg Davill
200c57f475 ecp5: Enable OPENDRAIN on differential outputs 2021-08-14 19:26:58 +09:30
gatecat
dd63764331
Merge pull request #791 from yrabbit/wip 
gowin: Add support for IOBUF and TBUF I/O modes. Change the constraint parser.
 2021-08-06 10:14:59 +01:00
YRabbit
3f959c7421 gowin: Change the constraint parser to support multiple options per line. Add support for IOBUF and TBUF I/O modes. 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2021-08-06 17:43:20 +10:00
gatecat
0c1ee5fad1
Merge pull request #789 from YosysHQ/gatecat/ecp5-pdp-outreg 
ecp5: Copy REGMODE in PDP mode to both A and B ports
 2021-08-03 13:05:01 +01:00
gatecat
5482b9a0c6 ecp5: Copy REGMODE in PDP mode to both A and B ports 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-08-02 20:58:45 +01:00
gatecat
ef1fbfc651
Merge pull request #787 from YosysHQ/gatecat/report 
Add JSON utilisation and timing report
 2021-07-30 14:29:55 +01:00
gatecat
8466985bc7
Merge pull request #788 from YosysHQ/gatecat/router2-ice40 
router2: Mark the destination as visited during backwards routing
 2021-07-30 11:10:21 +01:00
gatecat
b5a31d2e4e router2: Mark dest as visited during backwards routing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-30 09:14:46 +01:00
gatecat
42f48b6dc0 router2: Improve debugability of pip conflicts 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-29 13:04:59 +01:00
gatecat
d2007a386c common: Add JSON timing and utilisation report 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-29 12:53:23 +01:00
gatecat
4ac00af6fa basectx: Add a field to store timing results 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-29 12:52:13 +01:00
gatecat
0991003de9
Merge pull request #785 from YosysHQ/gatecat/nexus2glb2fabric 
nexus: Fix routeing of global clocks that also drive fabric
 2021-07-29 09:17:37 +01:00
gatecat
504199e70e nexus: Fix routeing of global clocks that also drive fabric 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-28 15:35:19 +01:00