We do a pre-pass on all the PLLs to place them before packing.
To place them:
- First pass with all the PADs PLLs since those can only fit at one
specific BEL depending on the input connection
- Second pass with all the dual outputs CORE PLLs. Those can go
anywhere where there is no conflicts with their A & B outputs and
used IO pins
- Third pass with the single output CORE PLLs. Those have the least
constrains.
During theses passes, we also check the validity of all their connections.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Instead of "patching" input_en, we completely separate config for
normal and LVDS pair.
- For normal pair, nothing changes
- For LVDS pairs, the IE/REN bits are always set as if the input buffer
are disabled. Then if input_en was set to 1 (i.e. the input is
actually for something), then we set the IoCtrl.LVDS bit.
- Also for LVDS, if input is used, pullups are forcibly disabled.
* When scanning for unused IOs, never process those part of a LVDS pair.
They will have been configured by the complement
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
We need to take into account the global networks that are already used
and possibly locked to know what we can promote since all networks
can't drive resets / clock-enables
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
During packing we replace them by standard SB_IO cells and create the
'fake' SB_GB that matches that IO site global buffer connection.
It's done in a separate pass because we need to make sure the nextpnr iob
have been dealt first so we have our final Bel location on the SB_IO.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Those are cells that are created mainly to handle the various sources a
global network can be driven from other than a user net.
When the flag is set, this means the global network usually driven by
this BEL is in fact driven by something else and so that SB_GB BEL and
matching global network can't be used.
This is also what gets used to set the extra bits during bitstream
generation.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
The icebox DB is a bit inconsistent in how global network connections
are represented. Here we make it appear consistent by creating ports
on the cells that can drive it.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
- Add a test for dual output PLL variant
- Make them handle the packet version of the cell
This will become useful for various tests during PLL rework
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Ideally we should first process all the PLL that are constrained somehow
(either explicitely or because they are PAD) and then free place the rest.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
