gatecat
19afb07370
interchange: Fix compile warnings
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-09-28 10:11:09 +01:00
gatecat
f03abe14d1
interchange: Skip IO ports in dedicated routing check
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These have already been dealt with in arch_pack_io
Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-12 11:43:18 +01:00
gatecat
8604b03008
interchange: Debug IO port validity check failures
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-12 11:40:23 +01:00
Alessandro Comodi
dc0819b01a
interchange: reduce run-time to check dedicated interconnect
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-07-08 16:51:23 +02:00
Alessandro Comodi
cfbd1dfa4d
interchange: fix dedicated interconnect exploration
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-06-30 20:04:23 +02:00
gatecat
b3882f8324
interchange: Fix dedicated interconnect check when site is the same
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-30 11:48:51 +01:00
gatecat
980a7013d2
interchange: Handle disconnected bel pins in dedicated interconnect
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-28 14:45:27 +01:00
gatecat
377f56c151
interchange: Cope with undriven nets in more places
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-14 10:58:42 +01:00
gatecat
ecc19c2c08
Using hashlib in arches
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 15:05:19 +01:00
Keith Rothman
8675945b26
Fix bug where DedicateInterconnect incorrectly allows some placement.
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This occurs when the driver pin and sink pin are part of the same site,
but not reachable with site routing only.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-30 13:24:39 -07:00
Keith Rothman
c8dccd3e7b
Implement debugging tools for site router.
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- Finishes implementation of SiteArch::nameOfPip and SiteArch::nameOfWire
- Adds "explain_bel_status", which should be an exhaustive diagnostic
of the status of a BEL placement.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-25 17:56:11 -07:00
gatecat
23413a4d12
Fix compiler warnings introduced by -Wextra
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-25 15:15:25 +00:00
Keith Rothman
a30043c8da
Fix assorted bugs in FPGA interchange.
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Fixes:
- Only use map constant pins during routing, and not during placement.
- Unmapped cell ports have no BEL pins.
- Fix SiteRouter congestion not taking into account initial expansion.
- Fix psuedo-site pip output.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:28 -08:00
Keith Rothman
184665652e
Finish dedicated interconnect implementation.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:28 -08:00
Keith Rothman
2fc353d559
Add initial logic for handling dedicated interconnect situations.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:28 -08:00
