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Author SHA1 Message Date
David Shah
2692c6f6cc
Merge pull request #437 from miek/lvcmos33d-drive 
ecp5: Allow setting drive strength for LVCMOS33D IOs
 2020-05-12 14:24:18 +01:00
Mike Walters
5b660e3432 ecp5: Allow setting drive strength for LVCMOS33D IOs 2020-05-12 14:19:37 +01:00
David Shah
e431d1a33f Add missing --top option 
Signed-off-by: David Shah <dave@ds0.me>
 2020-05-09 19:47:03 +01:00
David Shah
0faf07aac8 Merge branch 'rschlaikjer-rschlaikjer-mult18x18-register-timings' 2020-05-01 08:17:52 +01:00
David Shah
84327b634c ecp5: MULT18X18D timing fixes 
Signed-off-by: David Shah <dave@ds0.me>
 2020-05-01 08:17:29 +01:00
Ross Schlaikjer
a1160068c8
No cell delay for clocked MULT18X18D 2020-04-30 11:09:22 -04:00
Ross Schlaikjer
de6ddc470b
Further condense 2020-04-29 14:52:29 -04:00
Ross Schlaikjer
6e8082860e
Dedupe clock error check 2020-04-29 14:46:09 -04:00
Ross Schlaikjer
0043ae0807
Issue warning for mixed-mode inputs 2020-04-29 14:39:52 -04:00
Ross Schlaikjer
6625284950
Handle register timing case 2020-04-29 13:58:52 -04:00
Ross Schlaikjer
a4fa953740
Use registered port class on mult18x18 2020-04-29 11:08:53 -04:00
Ross Schlaikjer
5e763b1afc
Alter MULT18X18D timing db based on register config 
If the REG_INPUTA_CLK and REG_INPUTB_CLK values are set, then we should
use the faster setup/hold timings for the 18x8 multiplier.
Similarly, check the value of REG_OUTPUT_CLK for whether or not to use
faster timings for the output.

This is based on how I currently understand the registers to work - if
anyone knows the actual rules for when each timing applies please do
chime in to correct this implementation if necessary.

Along the same lines, this PR does not address the case when the
pipeline registers are enabled, since it is not clear to me how exactly
that affects the timing.
 2020-04-28 20:01:29 -04:00
David Shah
5c6b2cbafe
Merge pull request #433 from YosysHQ/dave/pyfixes 
python: Miscellaneous fixes
 2020-04-24 19:01:04 +01:00
David Shah
25938500d6 python: Also convert regular map keys to string 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-24 18:23:03 +01:00
David Shah
8f1683246e python: Improve general robustness during autocomplete 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-24 16:44:30 +01:00
David Shah
5024fc0690 python: Escape strings for autocomplete 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-24 16:41:13 +01:00
David Shah
fd099cef52 python: Wrap map IdString key when accessed by index 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-24 16:31:08 +01:00
David Shah
5e40589114
Merge pull request #432 from smunaut/fix_disconnect 
design_utils: Set port.net to null when disconnecting
 2020-04-24 15:35:33 +01:00
Sylvain Munaut
3573fcca80 design_utils: Set port.net to null when disconnecting 
Without this the python bindings can't actually connect anything else
to a disconnected port since the assert in connect_ports will think
it's still connected

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2020-04-24 16:13:07 +02:00
Miodrag Milanović
5cc8fe6c18
Merge pull request #428 from mmicko/master 
Better Boost support
 2020-04-20 14:36:18 +02:00
Miodrag Milanovic
93228f78d7 old boost support 2020-04-20 13:59:47 +02:00
David Shah
de00c00aac ecp5: Fix CSDECODE bitgen 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-15 20:25:56 +01:00
David Shah
4458251765
Merge pull request #426 from YosysHQ/dave/fix-pll2eclk 
ecp5: Use dedicated routing for ECLKs where possible
 2020-04-15 12:41:41 +01:00
David Shah
64d3e3e1e8 ecp5: Use dedicated routing for ECLKs where possible 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-14 19:20:13 +01:00
Miodrag Milanovic
96c14abd1f Add TRELLIS_PROGRAM_PREFIX 2020-04-11 22:05:30 +02:00
David Shah
3eff12a2a0
Merge pull request #424 from mmicko/program_prefix 
Support custom PROGRAM_PREFIX
 2020-04-10 14:00:00 +01:00
Miodrag Milanovic
bdea5d072d Support custom PROGRAM_PREFIX 2020-04-10 10:50:30 +02:00
David Shah
a8111bba83 ecp5: Fix routing bitgen for non-SERDES 'VCIB' tiles 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-10 08:25:16 +01:00
David Shah
ced336492c ecp5: Make hysteresis default-on for LVCMOS33 bidir as well as input 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-09 21:36:27 +01:00
David Shah
396dfb7d5e
Merge pull request #423 from rschlaikjer/rschlaikjer-regmode-timing-database 
Add support for REGMODE to DP16KD
 2020-04-07 20:02:29 +01:00
Ross Schlaikjer
3aecb3b08c
No need to fetch context 2020-04-07 14:44:19 -04:00
Ross Schlaikjer
fc591421f9
Change assert to error 2020-04-07 14:42:27 -04:00
Ross Schlaikjer
e46b990251
Rearrange bool algebra 2020-04-07 14:31:17 -04:00
Ross Schlaikjer
3257bdc8a1
Actually just move all the logic to ArchInfo 2020-04-07 14:11:49 -04:00
Ross Schlaikjer
0bdf1e05f1
Extract regmode configuration to ArchInfo 2020-04-07 14:03:55 -04:00
Ross Schlaikjer
c007463168
Change timing database lookup based on REGMODE value 2020-04-07 13:48:21 -04:00
David Shah
e8933f8519
Merge pull request #419 from garytwong/handle-opendrain 
Handle OPENDRAIN attribute.
 2020-04-07 09:44:40 +01:00
David Shah
571ad7d604
Merge pull request #421 from garytwong/fix-lpf-locate-assertion-failure 
Fix assertion failure on invalid LOCATE input.
 2020-04-07 09:44:22 +01:00
Gary Wong
ec1eea9990 Fix assertion failure on invalid LOCATE input. 
Trying to parse this invalid LPF syntax:

    LOCATE COMP "a" SITE "A1"
    IOBUF PORT "a" IO_TYPE=LVCMOS33;

(note missing semicolon on first line) gives an assertion failure in
strip_quotes, because the fifth token is scanned as "A1"IOBUF (without
a trailing quote).

Avoid the problem by detecting extraneous input and issuing a more
specific error.
 2020-04-05 21:42:45 -06:00
David Shah
70ccab4765
Merge pull request #420 from ironsteel/fix-reporting-of-default-router 
command.cc: Use correct constant for default router
 2020-04-04 09:13:27 +01:00
Rangel Ivanov
ef4a699b72 command.cc: Use correct constant for default router 
Otherwise --help reports that the default router is heap

Signed-off-by: Rangel Ivanov <rangelivanov88@gmail.com>
 2020-04-04 10:39:29 +03:00
Gary Wong
31e9fffadd Handle OPENDRAIN attribute. 2020-04-03 17:59:19 -06:00
David Shah
f9a76c56f7 ecp5: Allow use of IDDRXN and ODDRXN type primitives on the same pin 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-03 09:53:14 +01:00
David Shah
f09dfb028a
Merge pull request #418 from garytwong/usrmclk-works 
Remove comment about the USRMCLK primitive being untested.
 2020-04-03 08:31:26 +01:00
Gary Wong
8cc6a2fae5 Remove comment about the USRMCLK primitive being untested. 
Tested and verified working: the trivial configuration:

    module USRMCLK( USRMCLKI, USRMCLKTS );
        input USRMCLKI, USRMCLKTS;
    endmodule

    module top( input clk );
        reg[ 24:0 ] count = 0;

        always @( posedge clk ) begin
            count <= count + 1'b1;
        end

        USRMCLK mspi( .USRMCLKI( count[ 20 ] ), .USRMCLKTS( count[ 24 ] ) );
    endmodule

produces the expected output (toggling at high frequency, toggling
tri-state at lower frequency) on an LFE5U-85 when fed with an appropriate
clock.  See https://bayimg.com/AAnNKAAGO for an example.  The top
(magenta) trace is the MCLK line.
 2020-04-02 21:35:35 -06:00
David Shah
38efbf5dea
Merge pull request #417 from hackfin/master 
Enum/int compatibility for EHXPLLL parameters
 2020-04-02 16:28:35 +01:00
Martin
707289c8d6 Enum/int compatibility for EHXPLLL parameters 
- Lattice component EHXPLLL parameter compatibility, allowing to
  pass an int parameter for the enum (as expected by trellis tile)
  e.g. CLKOP_TRIM_DELAY : integer := 0;
 2020-04-02 14:25:00 +02:00
David Shah
98e2f9ea81 ice40: Derive oscillator frequency constraints 
Signed-off-by: David Shah <dave@ds0.me>
 2020-03-29 21:02:16 +01:00
David Shah
3d3b222e2a
Merge pull request #415 from smunaut/fix_iob_oe_reg 
ice40: Fix output register timing analysis for registered output enable
 2020-03-29 09:53:06 +01:00
Sylvain Munaut
bd68d6035c ice40: Fix output register timing analysis for registered output enable 
Wrong bits were being tested. [5:4] is what's controlling the output
enable path.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2020-03-29 10:27:42 +02:00