The dedicated router for clock wires now understands not only the IO
pins but also the rPLL outputs as clock sources.
This simple router sets an optimal route, so it is now the default
router. It can be disabled with the --disable-globals command line flag
if desired, but this is not recommended due to possible clock skew.
Still for GW1N-4C there is no good router for clock wires as there
external quartz resonator is connected via PLL.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
A simple router that takes advantage of the fact that in each cell with
DFFs their CLK inputs can directly connect to the global clock network.
Networks with a large number of such sinks are sought and then each
network is assigned to the available independent global clock networks.
There are limited possibilities for routing mixed networks, that is,
when the sinks are not only CLKs: in this case an attempt is made to use
wires such as SN10/20 and EW10/20, that is, one short transition can be
added between the global clock network and the sink.
* At this time, networks with a source other than the I/O pin are not
supported. This is typical for Tangnano4k and runber boards.
* Router is disabled by default, you need to specify option
--enable-globals to activate
* No new chip bases are required. This may change in the distant future.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
The model should be recognized by the partnumber, --family is needed
only if the same partnumbers belong to different models.
This is done in order to automatically generate parameters for calling
nextpnr from Gowin files without problems: there also only partnumber is
used and only in some cases the model is specified with the -name
parameter and GW1NZ-1 is not such a case.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
In the vendor IDE, there's a device family named GW1N-9C (which seems to
mean C revision of GW1N-9), in which the model numbers are all the same
with GW1N-9.
Add an option to nextpnr-gowin to allow manually specified family for
this situation.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* Items such as LUT, DFF, MUX, ALU, IOB are displayed;
* Local wires, 1-2-4-8 wires are displayed;
* The clock spines, taps and branches are displayed with some caveats.
For now, you can not create a project in the GUI because of possible
conflict with another PR (about GW1NR-9C support), but you can specify
the board in the command line and load .JSON and .CST in the GUI.
Although ALUs are displayed, but the CIN and COUT wires are not. This is
still an unsolved problem.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Instead of parsing the partnumber with a regular expression,
a simple table is used. This is done because the structure
of the partnumber changes as new features appear (e.g., ES instead of C6/I5)
This commit does not yet disable the very first regular expression check.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
