This uses a new data structure for net.users that allows gaps, so
removing a port from a net is no longer an O(n) operation on the number
of users the net has.
Signed-off-by: gatecat <gatecat@ds0.me>
This makes predictDelay be based on an arbitrary belpin pair rather
than a arc of a net based on cell placement. This way 'what-if'
decisions can be evaluated without actually changing placement;
potentially useful for parallel placement.
A new helper predictArcDelay behaves like the old predictDelay to
minimise the impact on existing passes; only arches need be updated.
Signed-off-by: gatecat <gatecat@ds0.me>
Clustering greatly helps the placer to identify and pack together
specific cells at the same site (e.g. LUT+FF), or cells that are chained through
dedicated interconnections (e.g. CARRY CHAINS)
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
During general routing, the only site pips that can be allowed are those
which connect a site wire to the routing interface.
This might be too restrictive when dealing with architectures that
require more than one site PIPs to route from a driver within a site to the routing
interface (which is something that should be allowed in the
interchange).
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
The pins created for tieing to Vcc were being named after the bel pin,
relying on the fact that Xilinx names cell and bel pins differently for
LUTs. This isn't true for Nexus devices which uses the same names for
both, and was causing a failure as a result.
This uses a "PHYS_" prefix that's highly unlikely to appear in a cell
pin name to disambiguate.
Signed-off-by: gatecat <gatecat@ds0.me>
Previous pseudo pips were the same cost as regular pips, but this is
definitely too fast, and meant that the router was prefering them.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This prevents the general router from routing through sites, which is
not legal in FPGA interchange.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
- Finishes implementation of SiteArch::nameOfPip and SiteArch::nameOfWire
- Adds "explain_bel_status", which should be an exhaustive diagnostic
of the status of a BEL placement.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
- Add IDEMPOTENT_CHECK define to perform some expected idempotent
operations more than once to verify they work as expected.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
For now just implements some inspection capabilities, and the site
router (for now) avoids inverted paths.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
