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Author SHA1 Message Date
gatecat
e546cd00de
Merge pull request #842 from yrabbit/delays 
gowin: Replace the zero delays with reasonable values.
 2021-10-09 21:52:18 +01:00
gatecat
8ad74edd66 router2: Disable criticality sorting towards end of routing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-10-09 20:56:45 +01:00
YRabbit
95217e7dd2 Merge branch 'master' into delays 2021-10-09 20:33:48 +10:00
YRabbit
bfe9cd548a gowin: Replace the zero delays with reasonable values. 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2021-10-09 20:26:18 +10:00
gatecat
520aec3ef4
Merge pull request #841 from Ravenslofty/lofty/mistral-cleanup 
mistral: clean up bel init slightly
 2021-10-08 18:00:13 +01:00
Lofty
4c8a8003d3 mistral: clean up bel init slightly 2021-10-08 15:21:21 +01:00
gatecat
b749ef5f56 hashlib: Support for std::array keys 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-10-07 17:05:16 +01:00
gatecat
74e7beb5e1
Merge pull request #839 from yrabbit/wide-luts 
gowin: add support for wide LUTs.
 2021-10-07 13:08:01 +01:00
YRabbit
c72ea15472 gowin: add support for wide LUTs. 
* A hardwired MUX within each logical cell is used.
  * The delay is equal 0.
  * No user placement constraints.
  * The output route contains dummy PIPs. They are ignored by gowin_pack, but it may be worth removing them.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2021-10-07 18:38:33 +10:00
gatecat
4f17a1711a
Merge pull request #837 from YosysHQ/gatecat/mistral-mlab-2 
mistral: Adding support for MLABs as memory
 2021-10-05 13:59:36 +01:00
gatecat
f5f7ef6864 mistral: Adding support for MLABs as memory 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-10-05 12:40:47 +01:00
gatecat
9c32e2d852
Merge pull request #836 from YosysHQ/gatecat/mistral-mlab 
mistral: Add bel pins for MLAB write port
 2021-10-03 18:49:42 +01:00
gatecat
fe31fba623 mistral: Add bel pins for MLAB write port 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-10-03 15:18:41 +01:00
gatecat
4d97e29999
Merge pull request #834 from YosysHQ/gatecat/cygwin 
Fix Cygwin build
 2021-10-01 17:11:59 +01:00
gatecat
211b6b6b06 Fix Cygwin build 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-10-01 12:40:56 +01:00
gatecat
5ae9eeba18
Merge pull request #833 from antmicro/interchange-fix-uninitialized-memory-bug 
interchange: fix uninitialized memory bug in cluster placement
 2021-10-01 12:38:05 +01:00
Alessandro Comodi
a3ba83fce3 interchange: fix uninitialized memory bug in cluster placement 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-10-01 11:53:56 +02:00
gatecat
7550b60069
Merge pull request #828 from YosysHQ/gatecat/interchange-warn-fix 
interchange: Enable Werror on CI and fix some compile warnings
 2021-09-30 11:05:32 +01:00
gatecat
bd137a8b50
Merge pull request #810 from antmicro/write-timing-report 
Timing report in JSON format
 2021-09-29 15:10:28 +01:00
Maciej Kurc
1db3a87c62 Code formatting 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-29 14:59:09 +02:00
Maciej Kurc
76f5874ffc Brought back printout of critical path source file references, added clk-to-q, source and setup segment types 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-29 10:16:45 +02:00
gatecat
8b3e6711bc
Merge pull request #830 from yrabbit/mistype 
Fix mistype.
 2021-09-29 06:40:30 +01:00
YRabbit
ddc368f0dd Fix mistype. 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2021-09-29 14:21:06 +10:00
Maciej Kurc
1ed692aca9 Shifted moving of data containers after printing 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-28 18:01:30 +02:00
Maciej Kurc
9018782eaa Added a commandline option controlled writeout of per-net timing details 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-28 17:42:51 +02:00
Maciej Kurc
a9df3b425f Added description of the JSON report structure. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-28 17:42:51 +02:00
Maciej Kurc
6deff56e83 Moved timing result report storage to the context, added its writeout to the current utilization and fmax report 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-28 17:42:51 +02:00
Maciej Kurc
c6dc1f535a Added reporting critical paths in JSON format 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-28 17:42:51 +02:00
Maciej Kurc
d8571b6c00 Decoupled critical path report generation from its printing 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-28 17:42:51 +02:00
Maciej Kurc
12adbb81b1 Switched to JSON format for timing analysis report 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-28 17:42:51 +02:00
Maciej Kurc
99ae5ef38e Added writing a CSV report with timing analysis of each net branch 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-28 17:42:51 +02:00
gatecat
19afb07370 interchange: Fix compile warnings 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-28 10:11:09 +01:00
gatecat
d89afc2aa6 ci: Enable -Werror for interchange arch 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-28 09:42:25 +01:00
gatecat
9d8d3bdbc4
Merge pull request #827 from YosysHQ/gatecat/idstring-in 
idstring: Add 'in' function from Yosys
 2021-09-27 22:03:11 +01:00
gatecat
0b0baf3446 idstring: Add 'in' function 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-27 19:18:40 +01:00
gatecat
535b2490c4
Merge pull request #812 from antmicro/MacroCells 
Convert macros to clusters for better placement
 2021-09-27 17:50:55 +01:00
Maciej Dudek
ea489f6d93 Fix small isses and code formatting 
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2021-09-27 16:16:33 +02:00
gatecat
9782a46a9b ci: Bump prjoxide version 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-24 19:21:44 +01:00
gatecat
d44b6acaa9
Merge pull request #826 from YosysHQ/gatecat/nexus-lutperm 
nexus: Add LUT permutation support
 2021-09-24 19:20:36 +01:00
gatecat
718ee441a0 nexus: Add resource cost overrides 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-24 19:19:26 +01:00
gatecat
ab6990f908 router2: Allow overriding resource costs 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-24 19:11:37 +01:00
gatecat
502fcff765 nexus: LUT permutation support 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-24 15:26:16 +01:00
Maciej Dudek
439ae9609b Break up macro_cluster_placement into smaller functions 
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2021-09-24 11:07:37 +02:00
Maciej Dudek
2de1ecfabe Update python-fpga-interchange to v0.0.20 
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2021-09-23 17:52:47 +02:00
Maciej Dudek
44def159cc Fix AC-3 algorithm 
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2021-09-23 17:15:09 +02:00
Maciej Dudek
b12119d8e8 Improve macro cluster placement 
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2021-09-23 15:43:23 +02:00
Maciej Dudek
94acf7a797 Change Cluster placement algorithm 
Use physical placement from device DB
It should reduce runtime

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2021-09-23 15:43:23 +02:00
Maciej Dudek
3cd459912a Adding MacroCell placement 
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2021-09-23 15:43:23 +02:00
Maciej Dudek
fdcfe8cd81 Adding support for MacroCells 2021-09-23 15:43:23 +02:00
gatecat
d9a71083e1
Merge pull request #825 from antmicro/chain_swap_fix 
Fix chain swap
 2021-09-23 14:10:46 +01:00