Keith Rothman
8773c645ca
[interchange] Prevent site router from generating incorrect LUTs.
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The previous logic tied LUT input pins to VCC if a wire was unplacable.
This missed a case where the net was present to the input of the LUT,
but a wire was still not legal. This case is now prevented by tying the
output of the LUT to an unused net.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-04-06 10:42:05 -07:00
Keith Rothman
0d41fff3a7
[interchange] Add crude pseudo pip model.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-04-06 10:42:05 -07:00
Keith Rothman
cc4f2b4516
Add some FIXME's around VCC assumption in LUT logic.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-25 17:20:13 -07:00
Keith Rothman
91ca5f110b
Re-work LUT mapping logic to only put VCC pins when required.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-25 17:20:13 -07:00
Keith Rothman
2cd5bacca0
Refactor header structures in FPGA interchange Arch.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-19 21:36:06 -07:00
Keith Rothman
351ca3b5ea
Use NEXTPNR_NAMESPACE macro's now that headers are seperated.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-15 18:49:12 +00:00
gatecat
fba71bd182
clangformat
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-03 10:39:47 +00:00
Keith Rothman
cfa449c3f3
Initial LUT rotation logic.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-26 11:01:22 -08:00
