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4,448 Commits 22 Branches 7 Tags 17 MiB
3281ca6717
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4448 Commits

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Author SHA1 Message Date
Miodrag Milanovic
3281ca6717 Add missing muxes for BRAM 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
437b57a510 Added getBelGlobalBuf 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
8c38e7ba61 Working BRAM 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
3a7770dca2 Add missing bel pins 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
19176ab597 Made PLL to work 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
1b3283fb7c Add constants for new bels 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
a79c2f3209 Add additional pic tiles 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
4b3ae70ca8 support DCC and use spine data 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
c04c961949 Import spine data 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
9121880c5f added a comment for constraining FF location 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
5e3fe3a4dc do not support FF on slice C when there is dpram 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
55518011e3 ramw and dram changes according to @gatecat 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
6ec3423405 LSRONMUX disable if not used by FF 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
510d92e01b cleanup FF and made DPRAM work in simple case 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
b6bb0cd5b8 Update CMakeList for machxo2 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
80c461bddd add write_bitstream to pybindings 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
05a191a014 Added LPF support 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
a0ba9afcba CCU2D is auto tied low 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
aacb36bf15 Use CCU2D cell 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
a00f810093 fix 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
6f85053b03 more like ecp5 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
3624fe90b2 one step closer 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
6508a0c267 This should not be here 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
153144022f More of making it inline 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
ca3d32e5ac make source more inline with ecp5 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
62ace58204 add missing bind and lutperm 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
7f8518d938 Import lutperm data 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
442142a47a typo fixes 2023-05-04 14:23:08 +02:00
Lofty
398b2ab569 bitstream emission update 2023-05-04 14:23:08 +02:00
Lofty
235a575267 port ecp5 split slice to machxo2 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
b033b915a6 Add bitgen for the rest of XO2 and XO3 2023-05-04 14:23:08 +02:00
Lofty
89c71bc8ac bitstream fixes for xo3 2023-05-04 14:23:08 +02:00
Miodrag Milanovic
80705e9bbb Support enabling XO3 and XO3D 2023-05-04 14:23:08 +02:00
YRabbit
051bdb12b3 gowin: fix style 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-04-20 08:35:50 +02:00
YRabbit
729757d55e gowin: fix style 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-04-20 08:35:50 +02:00
YRabbit
fdc2769259 gowin: add a common mechanism for placing ports 
If the port is in a different cell than the primitive, then use the alias mechanism.
Considerably compact code for OSC as an example.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-04-20 08:35:50 +02:00
YRabbit
71192dc7a3 gowin: Remove inherited code for ODDR(c) 
Implement ODDR(c) as part of IOLOGIC and remove all old code associated
with those primitives.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-04-14 09:23:00 +02:00
gatecat
b0a78de78f fabulous: Support for configurable LUT size 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-04-13 13:29:52 +02:00
YRabbit
62b8baa959 gowin: Fix style 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-04-12 14:35:17 +02:00
YRabbit
fddacb3dc1 gowin: implement IDES16 and OSER16 primitives 
These are very cumbersome primitives that take up two cells and
consequently 4 IOLOGIC bels.
The primitives are implemented for the chips that contain them and are
supported by apicula GW1NSR-4C, GW1NR-9 and GW1NR-9C.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-04-12 14:35:17 +02:00
gatecat
7557d33dc6 ecp5: Fix invalid accesses during certain IO packing cases 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-04-12 06:56:59 +02:00
gatecat
6455b5dd26 viaduct: Add support for GUIs 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-04-11 19:11:54 +02:00
YRabbit
9bcefe46a8 gowin: Add implementation of IDDR and IDDRC primitives 
Simple deserialization primitives are implemented for all supported boards.

Compatible with older apicula bases.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-04-06 08:41:54 +02:00
gatecat
23f2877dde fabulous: Fix bel names for pass bels in v2 format 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-04-05 15:45:18 +02:00
YRabbit
20b7f760d9 gowin: Add support for IDES primitives 
* placement of IDES4, IVIDEO, IDES8 and IDES10 primitives is supported;
* primitives are implemented for the GW1N-1, GW1NZ-1, GW1NSR-4C,
  GW1NR-9, GW1NR-9C chips;
* tricks required for IOLOGIC to work on one side of the -9 and -9C
  chips are taken into account;

Compatible with old apicula bases.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-04-04 10:00:08 +02:00
YRabbit
b36e8a3013 gowin: bugfix 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-03-23 12:37:53 +01:00
YRabbit
c52906e8bc gowin: Rename questionable ports 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-03-23 12:37:53 +01:00
YRabbit
38eb1f05ff gowin: Change the way errors are processed 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-03-23 12:37:53 +01:00
YRabbit
95ace0fade gowin: Add support for OSER primitives 
* placement of OSER4, OVIDEO, OSER8 and SER10 primitives is supported;
* primitives are implemented for the GW1N-1, GW1NZ-1, GW1NSR-4C,
  GW1NR-9, GW1NR-9C chips;
* the initial support for special HCLK clock wires is implemented to the
  extent necessary for OSER primitives to function;
* output to both regular IO and TLVDS_OBUF is supported;
* tricks required for IOLOGIC to work on one side of the -9 and -9C
  chips are taken into account;
* various edits, such as using idf() instead of the local buffer.

Compatible with old apicula bases.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-03-23 12:37:53 +01:00
gatecat
b3c33bd0ab ice40: Fix BRAM NegClk bitstream logic 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-03-20 18:54:57 +01:00