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78 Commits

Author SHA1 Message Date
gatecat
df7e26c1aa clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-03-09 17:12:59 +00:00
Maciej Dudek
191be632e2 nexus: DCCs cannot be cascaded 
This commit solves implicit cascading when clock signal drives DCC and logic

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2022-03-09 14:13:29 +01:00
gatecat
86699b42f6 Switch to potentially-sparse net users array 
This uses a new data structure for net.users that allows gaps, so
removing a port from a net is no longer an O(n) operation on the number
of users the net has.

Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-27 13:47:05 +00:00
gatecat
6a32aca4ac refactor: New member functions to replace design_utils 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-18 11:13:18 +00:00
gatecat
76683a1e3c refactor: Use constids instead of id("..") 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-16 17:09:54 +00:00
Dan Callaghan
5c30093360 nexus: reduce OSCA worst case to 7% 
The current version of Crosslink-NX Family Data Sheet lists the high
frequency oscillator maximum frequency as 481.5MHz (that is, 7% higher
than its nominal 450MHz):

https://www.latticesemi.com/-/media/LatticeSemi/Documents/DataSheets/CrossLink/FPGA-DS-02049-1-2-1-CrossLink-NX-Family.ashx?document_id=52780

Older documents listed a wider frequency range but ±7% is the range for
production parts.
 2022-02-10 15:48:06 +11:00
Maciej Kurc
3042f9e792 Fixed correction of Nexus OSCA frequency constraints 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-02-02 09:24:28 +01:00
Maciej Kurc
e51e82d6a9 Added honoring OSCA output frequency tolerance during constraints generation 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-01-28 13:51:10 +01:00
Maciej Kurc
18f71ace8c Removed the need for MULT36_CORE bel for implementing the MULTADDSUB9X9WIDE macro 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-01-25 12:08:52 +01:00
gatecat
35feb7ebba clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-12-12 13:02:39 +00:00
Maciej Kurc
41accf84ce Added checking if all FFs added to an existing cluster have matching configuration 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-11-23 15:16:26 +01:00
Maciej Kurc
238da79e52 Fixed potential issues with carry-chain cluster expansion, added a parameter controlling the ratio of FFs that got glued to carry-chain clusters. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-11-22 13:13:28 +01:00
Maciej Kurc
5bc97c94ae Added appending FFs to other existing LUT cluster types (carry, widefn) 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-11-22 10:23:24 +01:00
Maciej Kurc
086bcf0615 Added an option to control LUT and FF packing 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-11-22 10:23:24 +01:00
Maciej Kurc
d97f93ee88 Added clustering free LUTs and FFs 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-11-22 10:23:24 +01:00
gatecat
53e94653f3 nexus: Fix DSP macro placement 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-22 13:12:21 +01:00
Maciej Kurc
80e2f8a791 Added support for syn_useioff for enabling tri-state control FF integration into IOLOGIC. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-20 11:35:36 +02:00
Maciej Kurc
8ffd30cb2d Use correct names for IDDRX1_ODDRX1 FASM features 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-17 15:52:56 +02:00
Maciej Kurc
ef9eee6b15 Added automatic inference and integration of FFs driving T pin into IOLOGIC 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-17 13:49:35 +02:00
Maciej Kurc
6948d41616 Added handling of the case when tri-state control net bypasses SIOLOGIC bel 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-17 13:49:35 +02:00
gatecat
5686fdcf1c nexus: Basic packer and FASM support for I/ODDR 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-28 13:27:02 +01:00
gatecat
2ffb081442 Fixing old emails and names in copyrights 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-12 13:22:38 +01:00
gatecat
ecc19c2c08 Using hashlib in arches 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:19 +01:00
gatecat
579b98c596 Use hashlib for core netlist structures 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 14:27:56 +01:00
gatecat
c6fa1a179a nexus: Use new cluster API 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 12:25:32 +01:00
gatecat
08c7f97b1e nexus: Support for hard DPHY 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-08 15:59:18 +00:00
gatecat
7922b3bfc4 Replace DelayInfo with DelayPair/DelayQuad 
This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.

This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.

While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-19 11:31:33 +00:00
Keith Rothman
c99fbde0eb Mark IdString and IdStringList single argument constructors explicit. 
Single argument constructors will silently convert to that type.  This
is typically not the right thing to do.  For example, the nexus and
ice40 arch_pybindings.h files were incorrectly parsing bel name strings,
etc.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-04 16:38:07 -08:00
D. Shah
6566a011b4 nexus: Implement IdStringList for all arch object names 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-02 17:00:33 +00:00
D. Shah
5fc3e8e4d2 cleanup: Fix compiler warnings 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-01-28 15:02:08 +00:00
David Shah
2c6caf4a9a nexus: Add MULTADDSUB9X9WIDE support 
Signed-off-by: David Shah <dave@ds0.me>
 2020-12-08 15:49:48 +00:00
David Shah
f923d32620 nexus: Add support for initialised LRAM 
Signed-off-by: David Shah <dave@ds0.me>
 2020-12-07 11:57:10 +00:00
David Shah
270efdca85 nexus: Add basic LRAM support (no init) 
Signed-off-by: David Shah <dave@ds0.me>
 2020-12-02 17:07:34 +00:00
David Shah
86e6a2225c nexus: Add PLL support 
Signed-off-by: David Shah <dave@ds0.me>
 2020-12-02 15:01:46 +00:00
David Shah
b666c85824 nexus: Add support for deriving timing constraints in packer 
Signed-off-by: David Shah <dave@ds0.me>
 2020-12-02 09:44:17 +00:00
David Shah
df3c6dfe3e nexus: Preliminary integration of DSP timing data 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
e3b3201d53 nexus: Clocked MULTADDSUB36X36 fix 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
5cf7f01169 nexus: Add MULTADDSUB36X36 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
f795527454 nexus: Add MULTADDSUB18X18 support 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
edd719c5c5 nexus: ACC54 definitions 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
91d746cfc8 nexus: Add DSP pre-adder support 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
fcde8e2d56 nexus: Fix DSP signed ports 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
d8e748bc58 nexus: Refactor DSP macro splitting to make it more generic 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
30c65931b2 nexus: Add support for clocked MULT9X9s 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
9203181625 nexus: Support for unclocked 9x9 multiplies 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
d9a19897c4 nexus: More DSP primitive config 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
094bf419d4 nexus: Miscellaneous DSP infrastructure 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
90608f2c89 nexus: Add some infrastructure for DSP packing 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
530d6ce9e9 nexus: Add EBR timing analysis 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00
David Shah
9b89a82573 nexus: Add LUTRAM and WIDEFN9 timing support 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-30 08:45:28 +00:00