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Author SHA1 Message Date
Pepijn de Vos
354d497a57 only one type of dff per slice 2021-02-28 17:48:05 +01:00
gatecat
6689bfe923
Merge pull request #603 from litghost/fix_trival_bad_swap 
Prevent trival misplacements in placer1.
 2021-02-26 20:06:02 +00:00
Keith Rothman
c65ba121e0 Prevent trival misplacements in placer1. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-26 10:59:48 -08:00
gatecat
396af7470b
Merge pull request #602 from YosysHQ/gatecat/remove-unused-constr 
Remove unused advanced timing constraint API
 2021-02-26 11:03:21 +00:00
gatecat
b64f45a8ba Remove unused advanced timing constraint API 
This API was simply an attractive nuisance as no code was ever developed
to actually process timing constraints (other than clock constraints
which use a different API).

While I do want to consider basic false path support, among other
things, in the near future; I plan for this to use a new API that
doesn't add complexity to the BaseCtx/Context monstrosity and that is
easier to use on the timing analysis side.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-26 10:07:00 +00:00
gatecat
89928a0e6b
Merge pull request #599 from litghost/allow_router2_to_use_preroutes 
Allow router2 to use routed but not fixed arcs.
 2021-02-26 09:44:03 +00:00
gatecat
49fae99063
Merge pull request #601 from YosysHQ/no-default-Werror 
cmake: Don't enable any -Werror flags without opt-in
 2021-02-26 08:06:07 +00:00
whitequark
a0af4d8768
cmake: Don't enable any -Werror flags without opt-in. 2021-02-26 00:33:05 +00:00
Keith Rothman
c64a910151 Allow router2 to use routed but not fixed arcs. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-25 15:55:29 -08:00
gatecat
de107da5b3
Merge pull request #598 from YosysHQ/gatecat/compiler-flags 
Tighten up compiler flags
 2021-02-25 16:16:37 +00:00
gatecat
23413a4d12 Fix compiler warnings introduced by -Wextra 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-25 15:15:25 +00:00
gatecat
17183fff05 cmake: Enable -Wextra, and -Werror in some cases 
-Werror is not enabled by default, except on CI and for a few specific common traps, to avoid the inevitable breakages when new compiler versions add new diagnostics.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-25 11:05:26 +00:00
gatecat
ab8dfcfba4
Merge pull request #591 from litghost/add_constant_network 
Add constant network support to FPGA interchange arch
 2021-02-25 10:22:45 +00:00
gatecat
e2cdaa653c
Merge pull request #597 from litghost/add_dynamic_bitarray 
Add dynamic bitarray to common library.
 2021-02-24 18:22:16 +00:00
Keith Rothman
e0a4af09ed Bump tests submodule. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-24 09:09:23 -08:00
Keith Rothman
6d193ffd8b Fix some bugs found in review. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-24 09:09:06 -08:00
gatecat
4026082470 docs/archapi: Typo fixes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-24 15:28:33 +00:00
Keith Rothman
3650294e51 Add dynamic bitarray to common library. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 15:43:47 -08:00
gatecat
19ae97afd1
Merge pull request #595 from litghost/const_cell_info 
Change CellInfo in getBelPinsForCellPin to be const.
 2021-02-23 22:55:09 +00:00
gatecat
5de1978632
Merge pull request #596 from litghost/make_clang_format 
Run "make clangformat" to fix formatting in new Bits library.
 2021-02-23 22:49:35 +00:00
Keith Rothman
a30043c8da Fix assorted bugs in FPGA interchange. 
Fixes:
 - Only use map constant pins during routing, and not during placement.
 - Unmapped cell ports have no BEL pins.
 - Fix SiteRouter congestion not taking into account initial expansion.
 - Fix psuedo-site pip output.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:09:28 -08:00
Keith Rothman
184665652e Finish dedicated interconnect implementation. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:09:28 -08:00
Keith Rothman
5574455d2a Working FF example now that constant merging is done. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:09:28 -08:00
Keith Rothman
2fc353d559 Add initial logic for handling dedicated interconnect situations. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:09:28 -08:00
Keith Rothman
cd8297f54d Move RapidWright git URI back to upstream. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:09:28 -08:00
Keith Rothman
5c6e231412 Remove some signedness warnings. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:09:28 -08:00
Keith Rothman
46b38f8a40 Fix reference copy. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:09:27 -08:00
Keith Rothman
3ccb164f2a Run "make clangformat". 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:09:27 -08:00
Keith Rothman
15459cae91 Initial working constant network support! 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:09:27 -08:00
Keith Rothman
cf554f9338 Add constant network test case. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:09:27 -08:00
Keith Rothman
3e5a23ed5b Add tests to confirm constant routing import. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:09:27 -08:00
Keith Rothman
761d9d9229 Correct some bugs in the create_bba Makefile. 
Also add debug_test target to debug archcheck.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:09:27 -08:00
Keith Rothman
40df4f4f65 Add initial constant network support to FPGA interchange arch. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:09:27 -08:00
Keith Rothman
0758f68020 Update archapi.md with latest signature. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:08:59 -08:00
Keith Rothman
423a10bc31 Change CellInfo in getBelPinsForCellPin to be const. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 14:08:54 -08:00
Keith Rothman
bf458cbc5a Run "make clangformat" to fix new Bits library. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-23 13:55:05 -08:00
gatecat
85af066d4f
Merge pull request #594 from YosysHQ/gatecat/heap-tidying 
Tidying up HeAP
 2021-02-23 21:53:00 +00:00
gatecat
162793aa87 Refactor some common code to CellInfo methods 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-23 13:11:10 +00:00
gatecat
72b7a2e107 HeAP: Document legalise_placement_strict better 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-23 13:11:10 +00:00
gatecat
20f0ba9526 nexus: Fix getPipDelay returning negative after refactor 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-23 12:21:55 +00:00
gatecat
3b45174375 pyconsole: Avoid lockup when reading from stdin 
Create an empty temporary file for stdin; so reads fail rather than
locking up (otherwise doing help() would be enough to completely lock up
the GUI).

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-22 10:48:21 +00:00
gatecat
c0a7cff304 Demote the 'no clocks' warning to info and make clearer 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-20 20:15:52 +00:00
gatecat
6672f17d0a
Merge pull request #592 from YosysHQ/gatecat/rework-delay 
Replace DelayInfo with DelayPair and DelayQuad
 2021-02-20 10:51:57 +00:00
gatecat
e571c707b5 Update generic.md 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-20 10:51:30 +00:00
gatecat
130c5cc768 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-19 13:52:06 +00:00
gatecat
8ab36b4a05 python: Bindings for DelayPair and DelayQuad 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-19 13:41:40 +00:00
gatecat
7922b3bfc4 Replace DelayInfo with DelayPair/DelayQuad 
This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.

This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.

While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-19 11:31:33 +00:00
gatecat
8376db94a7 Add DelayPair and DelayQuad structures 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-19 10:58:16 +00:00
gatecat
5dcb59b13d
Merge pull request #576 from litghost/add_cell_bel_pin_mapping 
Complete FPGA interchange Arch to the point where it can route a wire
 2021-02-19 08:41:58 +00:00
Keith Rothman
c21e23b3eb Fix sign mismatch. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-18 14:08:22 -08:00