The GW1N-1 and GW1NZ-1 have a similar PLL, but the board with the former
chip is already very hard to buy, so let's experiment with a more
affordable chip.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
The rPLL primitive for the simplest chip (GW1N-1) in the family is
processed. All parameters of the primitive are passed on to gowin_pack,
and general-purpose wires are used for routing outputs of the primitive.
Compatible with older versions of apicula, but in this case will refuse
to place the new primitive.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
There is no need to multiply item names, it is a rudiment of my very
first addition to nextpnr.
Fully compatible with older versions of Apicula.
Note: the cosmetic changes in lines with RAM are not my initiative, but
the result of applying clang-format.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Refactor in order to detect networks that will be routed in a special
mode earlier. This makes it possible to mark the source of such networks
as a global buffer, thereby removing their influence on element
placement.
In addition, timing classes are set for some cells.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Gowin chips have a highly sophisticated system of long wires that are
wired to each cell and allow the clock or logic to spread quickly.
This commit implements some of the capabilities of the long wire system
for quadrants, leaving out the fine-tuning of them for each column.
To make use of the long wire system, the specified wire is cut at the
driver and a special cell is placed between the driver and the rest of
the wire.
* VCC and GND can not use long wires because they are in every cell and
there is no point in using a net
* Long wire numbers can be specified manually or assigned automatically.
* The route from the driver to the port of the new cell can be quite
long, this will have to be solved somehow.
* It might make sense to add a mechanism for automatically finding
candidates for long wires.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
This chip has a different default state for one type of I/O buffer ---
you have to explicitly switch it to the normal state by feeding VCC/VSS
to certain inputs.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Compatible with older versions of apicula bases.
Also small fixes and as the number of virtual Bels grows it is necessary
to assign them Z coordinate in a centralized way to avoid conflicts and
for this purpose introduced the BelZ enum.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
GSR is added automatically if it was not instantiated by the user explicitly.
Compatible with old apicula bases, the functionality does not work, but
the crash does not happen --- just a warning.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
This uses a new data structure for net.users that allows gaps, so
removing a port from a net is no longer an O(n) operation on the number
of users the net has.
Signed-off-by: gatecat <gatecat@ds0.me>
The new primitive appears as an amalgamation of two existing OBUF
primitives. Compatible with older versions of apicula, although, of
course, using TLVDS_OBUF with old databases will not bring the desired
result, but no crash.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Some models have I/O cells that are IOBUFs, and other types (IBUFs and
OBUFs) are obtained by feeding 1 or 0 to the OEN input. This is done
with general-purpose routing so it's best to do it here to avoid
conflicts.
For this purpose, in the new bases, these special cells are of type IOBS
(IOB Simplified).
The proposed changes are compatible with bases of previous versions of
Apycula and do not require changing .CST constraint files.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
- Both the mode used by yosys and all Gowin primitive modes are supported.
- The ALU always starts with a zero slice.
- The maximum length of the ALU chain is limited to one line of the chip.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* A hardwired MUX within each logical cell is used.
* The delay is equal 0.
* No user placement constraints.
* The output route contains dummy PIPs. They are ignored by gowin_pack, but it may be worth removing them.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Added support for the INS_LOC instruction in the constraints file
(.CST), which is used to specify object placement.
Expanded treatment of IO_LOC/IO_PORT constraints, which now can
be applied to both ports and IO buffers.
Port constraints have priority.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
