Commit Graph

7 Commits

Author SHA1 Message Date
gatecat
7922b3bfc4 Replace DelayInfo with DelayPair/DelayQuad
This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.

This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.

While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-19 11:31:33 +00:00
Keith Rothman
664407089b Add FPGA interchange frontend and backend.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-15 09:54:58 -08:00
Keith Rothman
9557047e5e Move all string data into BBA file.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-05 09:22:55 -08:00
Keith Rothman
22c3c9c303 Update copywrite headers.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:33 -08:00
Keith Rothman
0b911e484c Run "make clangformat".
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:33 -08:00
Keith Rothman
cd41c4001e Add initial updates to FPGA interchange arch for BEL buckets.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:33 -08:00
Keith Rothman
561b519716 Initial FPGA interchange (which is just a cut-down xilinx arch).
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:32 -08:00