Eddie Hung
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3f865f9049
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Fix Arch::estimateDelay()
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2018-09-02 23:38:53 -07:00 |
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Eddie Hung
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7e693ff27d
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Precompute pips too
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2018-09-02 19:06:20 -07:00 |
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Eddie Hung
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ca7eef26ac
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Wires now encapsulate segments
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2018-09-02 16:57:11 -07:00 |
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Eddie Hung
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df2f295545
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Apparently netgen needs SYNC_ATTR to be set
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2018-09-02 13:09:28 -07:00 |
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Eddie Hung
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82fbc551f8
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Fix DRC errors
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2018-08-21 22:58:20 -07:00 |
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Eddie Hung
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3a177c72c6
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Preserve packed LUT name as LUT_NAME parameter
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2018-08-21 22:24:14 -07:00 |
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Eddie Hung
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b658a39d73
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IOB -> IOB33; preserve FF init as DFF_INIT, use BUFGCTRL with PRESELECT_I0 in blinky
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2018-08-21 22:18:00 -07:00 |
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Eddie Hung
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5b6255abf1
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Fix LUT masks, add speedgrade, fix IOB type
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2018-08-20 21:50:06 -07:00 |
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Eddie Hung
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0a16e24c82
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create_ice_cell -> create_xc7_cell
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2018-08-20 19:29:04 -07:00 |
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Eddie Hung
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3e1085ecb5
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Combine IOB33S and IOB33M
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2018-08-20 19:25:54 -07:00 |
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Eddie Hung
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f7be783a32
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Escape flop names as well
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2018-08-20 19:21:53 -07:00 |
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Eddie Hung
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718f5b81f0
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Escape colons in config names
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2018-08-20 19:19:45 -07:00 |
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Eddie Hung
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699bd3ef5a
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Fix for leading '+', and use An for LUT masks
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2018-08-19 22:31:50 -07:00 |
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Eddie Hung
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a87f26b254
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Update comment
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2018-08-19 19:41:24 -07:00 |
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Eddie Hung
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dcc08b27cc
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Output unrouted nets into XDL
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2018-08-19 19:41:11 -07:00 |
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Eddie Hung
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07fb4702ce
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Populate LUT masks
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2018-08-19 19:16:24 -07:00 |
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Eddie Hung
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a7ccc01c45
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Use getBelType()
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2018-08-19 17:38:55 -07:00 |
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Eddie Hung
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17918b5992
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Fix for multiple id_SLICE_LUT6 per actual SLICE
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2018-08-17 23:05:12 -07:00 |
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Eddie Hung
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d05ac75fda
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Add basics for XDL exporter
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2018-08-17 21:52:34 -07:00 |
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Eddie Hung
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b8b9813056
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id_QUARTER_SLICE -> id_SLICE_LUT6, fix getBelLocation()
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2018-08-14 08:42:27 -07:00 |
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Eddie Hung
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72c785db0e
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Convert to use torc_info
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2018-08-12 22:09:16 -07:00 |
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Eddie Hung
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7b15569c69
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Use general pin names for QUARTER_SLICE
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2018-08-12 20:29:04 -07:00 |
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Eddie Hung
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56b7299cca
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{SLICEL,SLICEM} -> QUARTER_SLICE
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2018-08-12 20:21:03 -07:00 |
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Eddie Hung
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f6f20dce0c
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Rename ddb to torc
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2018-08-12 19:20:13 -07:00 |
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Eddie Hung
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8dedd7a83c
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Add stub for XDL output
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2018-08-12 19:07:33 -07:00 |
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Eddie Hung
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13e30a4eb1
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Add nextpnr-xc7 to gitignore
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2018-08-12 18:56:36 -07:00 |
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Eddie Hung
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0fe579f046
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Add torc symlink
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2018-08-12 18:56:25 -07:00 |
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Eddie Hung
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57c273898c
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Finishes placement now
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2018-08-11 22:24:13 -07:00 |
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Eddie Hung
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32f5346378
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Hacked blinky.ys yosys script
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2018-08-11 22:23:52 -07:00 |
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Eddie Hung
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67a0fa11e6
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Enable timing
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2018-08-11 21:36:23 -07:00 |
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Eddie Hung
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2bc7ffc2ea
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WIP
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2018-08-11 21:13:49 -07:00 |
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Eddie Hung
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8cddc49abc
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Starts placement onto all Xilinx sites
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2018-08-11 18:52:48 -07:00 |
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Eddie Hung
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45009ac09d
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Remove timing, remove wires
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2018-08-11 17:08:50 -07:00 |
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Eddie Hung
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74ff630922
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Tweak blinky.sh for xc7
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2018-08-11 16:01:15 -07:00 |
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Eddie Hung
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fbeb039f39
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Enable -pcf option but ignore
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2018-08-11 16:01:08 -07:00 |
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Eddie Hung
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8357417787
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Load Torc DDB
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2018-08-11 15:53:55 -07:00 |
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Eddie Hung
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6425032ec4
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Rip out ice40 stuff, put xc7z020 in
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2018-08-11 15:00:31 -07:00 |
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Eddie Hung
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a0d72a6f8e
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Add xc7 to supported arches
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2018-08-11 14:37:56 -07:00 |
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Eddie Hung
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d53658a079
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Copy ice40 into xc7
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2018-08-11 14:35:49 -07:00 |
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Eddie Hung
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2e02f2d616
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Merge pull request #48 from YosysHQ/placer_speedup
placer: low hanging speedups
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2018-08-11 09:27:50 -07:00 |
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Eddie Hung
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fc0496ec71
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Merge remote-tracking branch 'origin/master' into placer_speedup
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2018-08-10 19:51:35 -07:00 |
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Eddie Hung
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a41500a015
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Rework Arch::logicCellsCompatible() to take pointer + size, allowing use of std::array
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2018-08-10 19:50:27 -07:00 |
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Eddie Hung
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ded8308683
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std::vector::resize() not reserve()
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2018-08-09 21:03:07 -07:00 |
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Eddie Hung
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396cae5118
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Make containers static
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2018-08-09 20:53:33 -07:00 |
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Eddie Hung
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1514903ea9
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Get rid of map lookup by borrowing udata to use as index into vector
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2018-08-09 20:45:20 -07:00 |
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Eddie Hung
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e419b34027
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Try with vector
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2018-08-09 19:10:50 -07:00 |
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Miodrag Milanovic
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8b04a64629
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Fix compile warning
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2018-08-09 17:34:57 +02:00 |
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Miodrag Milanovic
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0696d62358
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Expose log_always that will be displayed disregarding quite flag
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2018-08-09 13:35:18 +02:00 |
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Miodrag Milanovic
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6b6a0c6d3c
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Added quiet mode for logging
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2018-08-09 13:28:21 +02:00 |
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Miodrag Milanovic
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8420cb4c80
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Fix MSVC compile
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2018-08-09 11:00:24 +02:00 |
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