Commit Graph

1392 Commits

Author SHA1 Message Date
Eddie Hung
3f865f9049 Fix Arch::estimateDelay() 2018-09-02 23:38:53 -07:00
Eddie Hung
7e693ff27d Precompute pips too 2018-09-02 19:06:20 -07:00
Eddie Hung
ca7eef26ac Wires now encapsulate segments 2018-09-02 16:57:11 -07:00
Eddie Hung
df2f295545 Apparently netgen needs SYNC_ATTR to be set 2018-09-02 13:09:28 -07:00
Eddie Hung
82fbc551f8 Fix DRC errors 2018-08-21 22:58:20 -07:00
Eddie Hung
3a177c72c6 Preserve packed LUT name as LUT_NAME parameter 2018-08-21 22:24:14 -07:00
Eddie Hung
b658a39d73 IOB -> IOB33; preserve FF init as DFF_INIT, use BUFGCTRL with PRESELECT_I0 in blinky 2018-08-21 22:18:00 -07:00
Eddie Hung
5b6255abf1 Fix LUT masks, add speedgrade, fix IOB type 2018-08-20 21:50:06 -07:00
Eddie Hung
0a16e24c82 create_ice_cell -> create_xc7_cell 2018-08-20 19:29:04 -07:00
Eddie Hung
3e1085ecb5 Combine IOB33S and IOB33M 2018-08-20 19:25:54 -07:00
Eddie Hung
f7be783a32 Escape flop names as well 2018-08-20 19:21:53 -07:00
Eddie Hung
718f5b81f0 Escape colons in config names 2018-08-20 19:19:45 -07:00
Eddie Hung
699bd3ef5a Fix for leading '+', and use An for LUT masks 2018-08-19 22:31:50 -07:00
Eddie Hung
a87f26b254 Update comment 2018-08-19 19:41:24 -07:00
Eddie Hung
dcc08b27cc Output unrouted nets into XDL 2018-08-19 19:41:11 -07:00
Eddie Hung
07fb4702ce Populate LUT masks 2018-08-19 19:16:24 -07:00
Eddie Hung
a7ccc01c45 Use getBelType() 2018-08-19 17:38:55 -07:00
Eddie Hung
17918b5992 Fix for multiple id_SLICE_LUT6 per actual SLICE 2018-08-17 23:05:12 -07:00
Eddie Hung
d05ac75fda Add basics for XDL exporter 2018-08-17 21:52:34 -07:00
Eddie Hung
b8b9813056 id_QUARTER_SLICE -> id_SLICE_LUT6, fix getBelLocation() 2018-08-14 08:42:27 -07:00
Eddie Hung
72c785db0e Convert to use torc_info 2018-08-12 22:09:16 -07:00
Eddie Hung
7b15569c69 Use general pin names for QUARTER_SLICE 2018-08-12 20:29:04 -07:00
Eddie Hung
56b7299cca {SLICEL,SLICEM} -> QUARTER_SLICE 2018-08-12 20:21:03 -07:00
Eddie Hung
f6f20dce0c Rename ddb to torc 2018-08-12 19:20:13 -07:00
Eddie Hung
8dedd7a83c Add stub for XDL output 2018-08-12 19:07:33 -07:00
Eddie Hung
13e30a4eb1 Add nextpnr-xc7 to gitignore 2018-08-12 18:56:36 -07:00
Eddie Hung
0fe579f046 Add torc symlink 2018-08-12 18:56:25 -07:00
Eddie Hung
57c273898c Finishes placement now 2018-08-11 22:24:13 -07:00
Eddie Hung
32f5346378 Hacked blinky.ys yosys script 2018-08-11 22:23:52 -07:00
Eddie Hung
67a0fa11e6 Enable timing 2018-08-11 21:36:23 -07:00
Eddie Hung
2bc7ffc2ea WIP 2018-08-11 21:13:49 -07:00
Eddie Hung
8cddc49abc Starts placement onto all Xilinx sites 2018-08-11 18:52:48 -07:00
Eddie Hung
45009ac09d Remove timing, remove wires 2018-08-11 17:08:50 -07:00
Eddie Hung
74ff630922 Tweak blinky.sh for xc7 2018-08-11 16:01:15 -07:00
Eddie Hung
fbeb039f39 Enable -pcf option but ignore 2018-08-11 16:01:08 -07:00
Eddie Hung
8357417787 Load Torc DDB 2018-08-11 15:53:55 -07:00
Eddie Hung
6425032ec4 Rip out ice40 stuff, put xc7z020 in 2018-08-11 15:00:31 -07:00
Eddie Hung
a0d72a6f8e Add xc7 to supported arches 2018-08-11 14:37:56 -07:00
Eddie Hung
d53658a079 Copy ice40 into xc7 2018-08-11 14:35:49 -07:00
Eddie Hung
2e02f2d616
Merge pull request #48 from YosysHQ/placer_speedup
placer: low hanging speedups
2018-08-11 09:27:50 -07:00
Eddie Hung
fc0496ec71 Merge remote-tracking branch 'origin/master' into placer_speedup 2018-08-10 19:51:35 -07:00
Eddie Hung
a41500a015 Rework Arch::logicCellsCompatible() to take pointer + size, allowing use of std::array 2018-08-10 19:50:27 -07:00
Eddie Hung
ded8308683 std::vector::resize() not reserve() 2018-08-09 21:03:07 -07:00
Eddie Hung
396cae5118 Make containers static 2018-08-09 20:53:33 -07:00
Eddie Hung
1514903ea9 Get rid of map lookup by borrowing udata to use as index into vector 2018-08-09 20:45:20 -07:00
Eddie Hung
e419b34027 Try with vector 2018-08-09 19:10:50 -07:00
Miodrag Milanovic
8b04a64629 Fix compile warning 2018-08-09 17:34:57 +02:00
Miodrag Milanovic
0696d62358 Expose log_always that will be displayed disregarding quite flag 2018-08-09 13:35:18 +02:00
Miodrag Milanovic
6b6a0c6d3c Added quiet mode for logging 2018-08-09 13:28:21 +02:00
Miodrag Milanovic
8420cb4c80 Fix MSVC compile 2018-08-09 11:00:24 +02:00