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291 Commits

Author SHA1 Message Date
Keith Rothman
c385321248 Add initial site router. 
This site router likely cannot handle the full problem space.  It may
need to be replaced with a more generalize approach as testing
continues.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:16 -08:00
Keith Rothman
a7421399f7 Working on standing up initial constraints system. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-17 12:03:16 -08:00
gatecat
399c24c805 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-17 10:45:23 +00:00
gatecat
da1ecf0813
Merge pull request #586 from litghost/add_cell_bel_mapping_only 
Add Cell -> BEL Pin maps to FPGA interchange arch.
 2021-02-17 10:16:45 +00:00
Keith Rothman
26a187e5eb Require --package when arch BBA contains multiple packages. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-16 14:00:01 -08:00
Keith Rothman
bb4fa7af5b [FPGA Interchange] Add Cell -> BEL Pin maps. 
This also expands the FPGA interchange Arch BBA to include placement
constraints, but doesn't implement them yet.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-16 09:37:19 -08:00
gatecat
c7c13cd95f Remove isValidBelForCell 
This Arch API dates from when we were first working out how to
implement placement validity checking, and in practice is little used by
the core parts of placer1/HeAP and the Arch implementation involves a
lot of duplication with isBelLocationValid.

In the short term; placement validity checking is better served by the
combination of checkBelAvail and isValidBelForCellType before placement;
followed by isBelLocationValid after placement (potentially after
moving/swapping multiple cells).

Longer term, removing this API makes things a bit cleaner for a new
validity checking API.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-16 13:31:36 +00:00
Keith Rothman
2c7ee44046 Move CMake logic into fpga-interchange-schema. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-15 09:54:58 -08:00
Keith Rothman
6b04fd1524 Small fixes from review. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-15 09:54:58 -08:00
Keith Rothman
664407089b Add FPGA interchange frontend and backend. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-15 09:54:58 -08:00
gatecat
1b6cdce925
Merge pull request #575 from YosysHQ/gatecat/belpin-2 
Support for cell pin to bel pin mappings
 2021-02-15 09:38:22 +00:00
Keith Rothman
82ab3c1aad Run "make clangformat". 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-12 10:31:05 -08:00
Keith Rothman
8a860857ea Remove capnp and libz for XDC parser PR. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-12 10:31:05 -08:00
Keith Rothman
c96d0f225c Refactor XDC parser into a little class for testing purposes. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-12 10:31:04 -08:00
Keith Rothman
d987bd2997 Add unknown handles to convert [0] to "[0]". 
Tcl reads something like "set port [get_ports x[0]]" as "invoke proc 0
with zero arguments", rather than just "[0]".  To prevent exposing
non-Tcl users this, "[<number>]" just return themselves.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-12 10:31:04 -08:00
Keith Rothman
a0bd313139 Add FPGA interchange XDC parser. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-12 10:31:04 -08:00
Keith Rothman
99e397000c Add getBelHidden and add some missing "override" statements. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-11 14:58:02 -08:00
gatecat
85bb108ba4 Add getBelPinsForCellPin to Arch API 
This is a basic implementation, without considering "M of N"
arrangements (e.g. for LUT permuation where you only want to route to 1
out of 4/6 sinks) or using a type other than IdString to identify bel
pins.

But this is also enough to start working out where in nextpnr will break
due to removing the 1:1 cell:bel pin cardinality, as a next step.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-10 11:54:54 +00:00
D. Shah
9deb9e6e85 interchange: Base on ArchAPI 
Signed-off-by: D. Shah <dave@ds0.me>
 2021-02-08 10:41:03 +00:00
Keith Rothman
a0ee42833b Add RelSlice::ssize and use it when comparing with signed ints. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-05 10:12:13 -08:00
Keith Rothman
9557047e5e Move all string data into BBA file. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-05 09:22:55 -08:00
Keith Rothman
ca32e935a6 Use RelSlice instead of RelPtr in cases where sizes are present. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-04 16:38:34 -08:00
Keith Rothman
f1ee2fde58 Update APIs to conform to style guide. 
- Change non-Arch methods to snake_case
 - Adds some utility functions to for accessing bel_data.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-04 16:38:34 -08:00
Keith Rothman
9afa8a9bea Remove unused method getReservedWireNet. 
This was a holdover from the nextpnr-xilinx arch.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-04 16:38:33 -08:00
Keith Rothman
22c3c9c303 Update copywrite headers. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-04 16:38:33 -08:00
Keith Rothman
58c90184f6 Correct some typos. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-04 16:38:33 -08:00
Keith Rothman
d8fa9d7f36 Fix warnings with signed/unsigned. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-04 16:38:33 -08:00
Keith Rothman
d4f66a73c1 Fix fpga_interchange/README.md duplicate patch statement. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-04 16:38:33 -08:00
Keith Rothman
90ece77f8d Fix URLs in Markdown. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-04 16:38:33 -08:00
Keith Rothman
dc47c6d9ec Add empty constids.inc for build. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-04 16:38:33 -08:00
Keith Rothman
0b911e484c Run "make clangformat". 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-04 16:38:33 -08:00
Keith Rothman
149087b880 Add README about initial state of FPGA interchange implementation. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-04 16:38:33 -08:00
Keith Rothman
78737ab01d Update FPGA interchange to use IdStringList. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-04 16:38:33 -08:00
Keith Rothman
4a62c8c2eb Start adding data for placement constraint solving. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-04 16:38:33 -08:00
Keith Rothman
5c16c5024d Debug BEL bucket data. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-04 16:38:33 -08:00
Keith Rothman
cd41c4001e Add initial updates to FPGA interchange arch for BEL buckets. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-04 16:38:33 -08:00
Keith Rothman
67dc19bb57 Address review comments. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-04 16:38:33 -08:00
Keith Rothman
5a89dc58e1 Fix BBA import bugs. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-04 16:38:33 -08:00
Keith Rothman
1dd24f6461 Assorted fixes to new FPGA interchange based arch. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-04 16:38:33 -08:00
Keith Rothman
6e68e8f097 Initial compiling version. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-04 16:38:32 -08:00
Keith Rothman
561b519716 Initial FPGA interchange (which is just a cut-down xilinx arch). 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2021-02-04 16:38:32 -08:00