Miodrag Milanovic
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796d648995
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Merge remote-tracking branch 'origin/master' into mmicko/ecp5_gui
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2019-12-28 13:54:06 +01:00 |
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Miodrag Milanovic
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436260e47e
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move bel creation to gfx.cc
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2019-12-15 09:21:58 +01:00 |
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Miodrag Milanovic
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fb27f1a031
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fix formating
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2019-12-14 16:40:27 +01:00 |
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Miodrag Milanovic
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ebbfb6375d
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more new wires added
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2019-12-14 09:18:24 +01:00 |
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Miodrag Milanovic
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19eb16045f
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ebr, mult and alu nice display
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2019-12-14 08:21:02 +01:00 |
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Miodrag Milanovic
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7fd856b866
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clangformat run
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2019-12-08 09:33:06 +01:00 |
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Miodrag Milanovic
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275805d78f
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display IOs properly
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2019-12-07 19:06:10 +01:00 |
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Miodrag Milanovic
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401bee6111
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More bels show properly
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2019-12-07 18:52:33 +01:00 |
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Miodrag Milanovic
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76d2a3f0db
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add dcca bels and dummy parts for other bels
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2019-12-07 17:41:22 +01:00 |
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Miodrag Milanovic
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74f2c4a73b
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more pips, and valid mapping
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2019-11-10 15:24:06 +01:00 |
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Miodrag Milanovic
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f6d74cb7a9
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Draw some pips, fixed H6 and V6
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2019-11-09 13:12:20 +01:00 |
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David Shah
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475fcd4425
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ecp5: Add an error for out-of-sync constids and bba
Signed-off-by: David Shah <dave@ds0.me>
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2019-10-26 20:38:28 +01:00 |
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David Shah
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36c07a0f45
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ecp5: Fix routing to shared DSP control inputs
Signed-off-by: David Shah <dave@ds0.me>
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2019-10-25 09:37:13 +01:00 |
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Miodrag Milanovic
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49760a9ea8
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Show V02/V06/H02/H06
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2019-10-25 09:28:08 +02:00 |
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Miodrag Milanovic
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0d2ae5cc9d
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Split graphics calls for wires into gfx.cc
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2019-10-20 11:12:26 +02:00 |
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Miodrag Milanovic
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e9ae0cf7ce
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muxes only together with slices
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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eaf760768b
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Remove not used line
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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e69bb4c077
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Simplify layout of elements
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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3b01d2fbce
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fix slice wire
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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399a137a77
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bound signals
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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8c79044d43
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more wires between switchboxes
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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4cbdc388b8
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Add more types of wires
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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966d0dec19
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finixed slice wires
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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74da9cc424
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wd wires
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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4b79050ef4
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Fix look of some wires
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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a59faa8df0
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Add output wires
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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07a8022a1f
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fix mux display
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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a11cc8791b
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set wire active flag
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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3da7af9f02
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clk and lsr muxes
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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0b4ced96ec
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draw rest of slice wires and more from switchbox
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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3e117ce792
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Optimize
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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49b12a828a
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Add other side of slice wires
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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1ae64d7bf5
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Display rest of slice input wires
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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f7a6d4dc06
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Start adding visible wires
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2019-10-20 09:41:48 +02:00 |
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Miodrag Milanovic
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bfbb6dbf69
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Draw swbox, smaller slices, proper io
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2019-10-20 09:41:30 +02:00 |
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David Shah
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9b83e67460
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ecp5: Preparations for new IO bels
Signed-off-by: David Shah <dave@ds0.me>
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2019-10-09 10:55:10 +01:00 |
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David Shah
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d04e5954a6
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ecp5: Adding support for 36-bit wide PDP RAMs
Signed-off-by: David Shah <dave@ds0.me>
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2019-10-01 12:01:33 +01:00 |
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David Shah
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9f9920f92b
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ecp5: Add full part name to bitstream header
Signed-off-by: David Shah <dave@ds0.me>
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2019-08-27 14:36:20 +01:00 |
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David Shah
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78f86ce67a
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ecp5: Add GSR/SGSR support
Signed-off-by: David Shah <dave@ds0.me>
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2019-08-27 13:14:41 +01:00 |
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David Shah
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c70f87e4c5
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Merge pull request #309 from YosysHQ/dsptiming
ecp5: Conservative analysis of comb DSP timing
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2019-08-09 10:27:15 +01:00 |
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David Shah
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661237eb64
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ecp5: Add --out-of-context for building hard macros
Signed-off-by: David Shah <dave@ds0.me>
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2019-08-07 14:22:47 +01:00 |
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David Shah
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ec48f8f464
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ecp5: New Property interface
Signed-off-by: David Shah <dave@ds0.me>
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2019-08-05 17:22:37 +01:00 |
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David Shah
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2da41a66c7
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ecp5: Conservative analysis of comb DSP timing
Signed-off-by: David Shah <dave@ds0.me>
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2019-07-08 15:09:54 +01:00 |
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Miodrag Milanovic
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ec47ce2320
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Merge master
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2019-06-25 18:14:51 +02:00 |
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David Shah
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df8688c227
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ecp5: Delay tweaking for lower speed grades
Signed-off-by: David Shah <dave@ds0.me>
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2019-06-21 10:55:23 +01:00 |
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David Shah
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7ae64b9477
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ecp5: Reduce cfg.criticalityExponent for now
Signed-off-by: David Shah <dave@ds0.me>
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2019-06-21 10:20:46 +01:00 |
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Miodrag Milanovic
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36ccc22fc9
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Use flags for each step
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2019-06-14 09:59:04 +02:00 |
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Miodrag Milanovic
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d9b0bac248
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Save top level attrs and store current step
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2019-06-07 16:11:11 +02:00 |
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Miodrag Milanovic
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78e6631f76
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Cleanup
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2019-06-07 13:49:19 +02:00 |
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Miodrag Milanovic
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54175f9187
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No need for this one
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2019-06-07 13:24:16 +02:00 |
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